公开(公告)号：JPH08186123A

公开(公告)日：1996-07-16

申请号：JP31686694

申请日：1994-12-20

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： RI KIKOU ,  RI SHINKOU

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/732

Abstract: PURPOSE: To minimize the base-collector and base-emitter parasitic junction capacitance by providing a base electrode, an emitter electrode and a collector electrode connected, respectively, with an external base region, an emitter region and a collector region thereby equalizing the operational characteristics in both directions. CONSTITUTION: A thin film for base electrode or an external base region 24 is composed of polysilicon filling a trench. An oxide 34 is deposited between the external base region 24 filling a trench region and a substrate 21. A conductive base region 27 is formed in the center of a columnar structure. Electrodes 29 are formed in the external base region 24, the emitter 28 region and a part of the collector region 23. In this regard, a conductive thin film 26 wider than the emitter 28 may be formed in order to facilitate formation of a contact hole for interconnection between the emitter 28 and the emitter electrode.

公开(公告)号：JPH0193159A

公开(公告)日：1989-04-12

申请号：JP17827188

申请日：1988-07-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIN KOUSHIYU ,  SAI SOUKUN ,  GU YOUSHIYO ,  KIN JIYOKAN ,  RI SHINKOU

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732

Abstract: PURPOSE: To ensure high speed and high integration characteristics by simultaneously fabricating a high speed bipolar transistor with self alignment of polycrystalline Si and a high integration CMOS device using one wafer. CONSTITUTION: The surface of a P type substrate (Si wafer) 1 is ion implanted with As using a buried layer mask to form N type buried layers 2, 3 and an N type epitaxial layer 4 is grown over the entire surface of the substrate. The layer 4 is ion implanted with B using an oxide film mask to form a P type well 5, and after the oxide film is formed, a Si3 N4 film is deposited. The inside of the layer 4 is ion implanted with B to form a P type junction isolation layer 6, and an oxide film is grown, and further a device isolation region 7 and an insulating layer 8 are formed. B, P are implanted using a mask to form a P type base region 9 and an N type collector region 10, and As is implanted to form an N type polycrystal Si layer 11 on which an oxide film 12 is deposited. Then, gates 13, 14, an emitter 15, and a collector 16 are simultaneously formed. Further, sources/drains 17, 18 and 19, 20 are formed.

公开(公告)号：JPH0738066A

公开(公告)日：1995-02-07

申请号：JP33820391

申请日：1991-12-20

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： RI KIKOU ,  SAI SOUKUN ,  YO JUNICHI ,  KIN CHINSHIYOU ,  RI SHINKOU

IPC: H01L27/10 ,  H01L21/337 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/808

Abstract: PURPOSE: To provide a product having a vertical structure for realizing a highly integrated structure with reduced area of basic cells by arranging switching junction field transistors and storing capacitors to form the vertical structure. CONSTITUTION: Switching junction field transistors are formed on a semiconductor substrate 1, and storing capacitors are stacked on the junction field transistors to arrange these transistors and capacitors in the form of a vertical structure. The transistor has a gate region at a trench sidewall bottom formed by etching the substrate 1, word line 10a insulated from other element word lines through an insulation film 13 and active region 16 on the substrate 1. The storing capacitor has a storage node on a drain junction region, dielectric film 18 on the top of this node, and polysilicon film 19 for a plate electrode which is insulated from the storage node through an oxide film.

公开(公告)号：JPS6273667A

公开(公告)日：1987-04-04

申请号：JP14797986

申请日：1986-06-24

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： SAI SOUKUN ,  RI SHINKOU

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/285 ,  H01L21/308 ,  H01L21/331 ,  H01L29/70 ,  H01L29/732