公开(公告)号：US20130219713A1

公开(公告)日：2013-08-29

申请号：US13663663

申请日：2012-10-30

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Jun-Chung Hsu ,  Chi-Ming Lin ,  Tso-Hung Yeh ,  Ya-Hsiang Chen

IPC: H05K3/46

CPC classification number: H05K3/4644 ,  H05K3/24 ,  H05K3/4682 ,  H05K2201/0317 ,  H05K2201/0347 ,  H05K2203/072 ,  Y10T29/49155

Abstract: A method of manufacturing a laminate circuit board with a multilayer circuit structure which includes the steps of forming a metal layer on a substrate, patterning the metal layer to form a circuit metal layer, forming a nanometer plating layer on the circuit metal layer, forming a cover layer to cover the substrate and the nanometer plating layer, forming through holes in the cover layer to generate openings exposing part of the nanometer plating layer, and finally forming a second metal layer on the cover layer to fill up the openings is disclosed. The nanometer plating layer is used to obtain same effect of previously roughening by chemical bonding, such that no circuit width is reserved for compensation, and the density of the circuit increases such that much more dense circuit can be implemented.

Abstract translation: 一种制造具有多层电路结构的叠层电路板的方法，包括以下步骤：在基板上形成金属层，图案化金属层以形成电路金属层，在电路金属层上形成纳米电镀层，形成 盖层覆盖基板和纳米镀层，在盖层中形成孔，以产生露出纳米镀层的一部分的开口，最后在覆盖层上形成第二金属层以填充开口。 纳米电镀层用于通过化学键合获得与之前的粗糙化相同的效果，使得没有电路宽度被保留用于补偿，并且电路的密度增加，使得可以实现更加密集的电路。

公开(公告)号：US20130224513A1

公开(公告)日：2013-08-29

申请号：US13663141

申请日：2012-10-29

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Jun-Chung Hsu ,  Chi-Ming Lin ,  Tso-Hung Yeh ,  Ya-Hsiang Chen

IPC: H05K1/03

CPC classification number: H05K3/28 ,  H05K3/243 ,  H05K3/4644 ,  H05K2201/0347

Abstract: A laminate circuit board with a multi-layer circuit structure which includes a substrate, a first circuit metal layer, a second circuit metal layer, a first nanometer plating layer, a second nanometer plating layer and a cover layer is disclosed. The first circuit metal layer is embedded in the substrate or formed on at least one surface of the substrate which is smooth. The first nanometer plating layer with a smooth surface overlaps the first circuit metal layer. The second nanometer plating layer is formed on the other surface of the substrate and fills up the opening in the cover layer to electrically connect the first circuit metal layer. The junction adhesion is improved by the chemical bonding between the nanometer plating layer and the cover layer/the substrate. Therefore, the circuit metal layer does not need to be roughened and the density of the circuit increases.

Abstract translation: 公开了一种具有多层电路结构的叠层电路板，其包括基板，第一电路金属层，第二电路金属层，第一纳米镀层，第二纳米镀层和覆盖层。 第一电路金属层嵌入衬底中或形成在衬底的平滑的至少一个表面上。 具有平滑表面的第一纳米镀层与第一电路金属层重叠。 第二纳米镀层形成在基板的另一个表面上，并填满覆盖层中的开口以电连接第一电路金属层。 通过纳米电镀层和覆盖层/基板之间的化学键合来改善连接粘附。 因此，电路金属层不需要粗糙化，电路密度增加。

公开(公告)号：US08754328B2

公开(公告)日：2014-06-17

申请号：US13663141

申请日：2012-10-29

Applicant: Kinsus Interconnect Technology Corp.

Inventor： Jun-Chung Hsu ,  Chi-Ming Lin ,  Tso-Hung Yeh ,  Ya-Hsiang Chen

IPC: H02G15/00 ,  H05K1/11

CPC classification number: H05K3/28 ,  H05K3/243 ,  H05K3/4644 ,  H05K2201/0347

Abstract: A laminate circuit board with a multi-layer circuit structure which includes a substrate, a first circuit metal layer, a second circuit metal layer, a first nanometer plating layer, a second nanometer plating layer and a cover layer is disclosed. The first circuit metal layer is embedded in the substrate or formed on at least one surface of the substrate which is smooth. The first nanometer plating layer with a smooth surface covers the first circuit metal layer. The second nanometer plating layer is formed on the other surface of the substrate and fills up the opening in the cover layer to electrically connect the first circuit metal layer. The junction adhesion is improved by the chemical bonding between the nanometer plating layer and the cover layer/the substrate. Therefore, the circuit metal layer does not need to be roughened and the density of the circuit increases.

Abstract translation: 公开了一种具有多层电路结构的叠层电路板，其包括基板，第一电路金属层，第二电路金属层，第一纳米镀层，第二纳米镀层和覆盖层。 第一电路金属层嵌入衬底中或形成在衬底的平滑的至少一个表面上。 具有光滑表面的第一纳米镀层覆盖第一电路金属层。 第二纳米镀层形成在基板的另一个表面上，并填满覆盖层中的开口以电连接第一电路金属层。 通过纳米电镀层和覆盖层/基板之间的化学键合来改善连接粘附。 因此，电路金属层不需要粗糙化，电路密度增加。