中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

45 records (took 0.024 seconds)

    METHOD AND SYSTEM FOR CENTERING WAFER ON CHUCK
    2.
    发明申请
    METHOD AND SYSTEM FOR CENTERING WAFER ON CHUCK 审中-公开
    用于在卡盘上定中晶片的方法和系统

    公开(公告)号：WO2010067284A2

    公开(公告)日：2010-06-17

    申请号：PCT/IB2009055503

    申请日：2009-12-04

    Applicant: LAM RES CORP ,  O'NEILL ROBERT GRIFFITH ,  LUQUE JORGE ,  CHOU SHANG-I ,  SINGH HARMEET

    Inventor： O'NEILL ROBERT GRIFFITH ,  LUQUE JORGE ,  CHOU SHANG-I ,  SINGH HARMEET

    IPC: H01L21/68 ,  H01L21/687

    CPC classification number: H01L21/67748 ,  G01N21/9501 ,  G01N2021/8864 ,  H01L21/67259 ,  H01L21/68

    Abstract: A wafer handling mechanism is operated to place a wafer on a chuck. A chucking force is then applied to the wafer, whereby wafer support features of the chuck transfer a defect pattern onto a surface of the wafer. The surface of the wafer is analyzed by a defect metrology tool to obtain a mapping of the defect pattern transferred onto the surface of the wafer. A center coordinate of the chuck within a coordinate system of the wafer is determined by analyzing the defect pattern as transferred to the surface of the wafer. A spatial offset between the center coordinate of the chuck and the center of the wafer is determined. The spatial offset is used to adjust the wafer handling mechanism so as to enable alignment of the center of the wafer to the center coordinate of the chuck.

    Abstract translation: 操作晶片处理机构以将晶片放置在卡盘上。 然后将夹紧力施加到晶片，由此夹盘的晶片支撑特征将缺陷图案转移到晶片的表面上。 通过缺陷度量工具分析晶片的表面，以获得转移到晶片表面上的缺陷图案的映射。 通过分析传送到晶片表面的缺陷图案来确定晶片的坐标系内的卡盘的中心坐标。 确定卡盘的中心坐标和晶片的中心之间的空间偏移。 空间偏移用于调整晶片处理机构，以使晶片的中心能够对准卡盘的中心坐标。

    METHOD AND APPARATUS OF HALOGEN REMOVAL
    7.
    发明申请
    METHOD AND APPARATUS OF HALOGEN REMOVAL 审中-公开
    杀虫剂的方法和装置

    公开(公告)号：WO2011056484A3

    公开(公告)日：2011-08-04

    申请号：PCT/US2010053858

    申请日：2010-10-22

    Applicant: LAM RES CORP ,  SINGH HARMEET ,  SANT SANKET ,  CHOU SHANG-I ,  VAHEDI VAHID ,  CASAES RAPHAEL ,  RAMACHANDRAN SEETHARAMAN

    Inventor： SINGH HARMEET ,  SANT SANKET ,  CHOU SHANG-I ,  VAHEDI VAHID ,  CASAES RAPHAEL ,  RAMACHANDRAN SEETHARAMAN

    IPC: H01L21/302 ,  H01L21/677

    CPC classification number: H01L21/02057 ,  H01L21/67017 ,  H01L21/67115 ,  H01L21/6719 ,  H01L21/67201 ,  H01L21/67207

    Abstract: A wafer is provided into an entrance load lock chamber. A vacuum is created in the entrance load lock chamber. The wafer is transported to a processing tool. The wafer is processed in a process chamber to provide a processed wafer, wherein the processing forms halogen residue. A degas step is provided in the process chamber after processing the wafer. The processed wafer is transferred into a degas chamber. The processed wafer is treated in the degas chamber with UV light and a flow of gas comprising at least one of ozone, oxygen, or H2O. The flow of gas is stopped. The UV light is stopped. The processed wafer is removed from the degas chamber.

    Abstract translation: 将晶片设置在入口加载锁定室中。 在入口装载锁定室中产生真空。 晶片被输送到处理工具。 在处理室中处理晶片以提供经处理的晶片，其中处理形成卤素残余物。 在处理晶片之后，在处理室中提供脱气步骤。 将经处理的晶片转移到脱气室中。 处理的晶片在脱气室中用UV光和包含臭氧，氧气或H 2 O中的至少一种的气体流进行处理。 停止气体流动。 UV灯停止。 将经处理的晶片从脱气室中取出。

    METHODS OF FAULT DETECTION FOR MULTIPLEXED HEATER ARRAY
    8.
    发明申请
    METHODS OF FAULT DETECTION FOR MULTIPLEXED HEATER ARRAY 审中-公开
    多路加热器阵列故障检测方法

    公开(公告)号：WO2012054198A3

    公开(公告)日：2012-06-21

    申请号：PCT/US2011053558

    申请日：2011-09-28

    Applicant: LAM RES CORP ,  SINGH HARMEET

    Inventor： SINGH HARMEET

    IPC: H01L21/205 ,  H01L21/66

    CPC classification number: H05B1/0233 ,  H01L21/67109 ,  H01L21/67288

    Abstract: Abstract Described herein is a method of detecting fault conditions in a multiplexed multi-heater-zone heating plate for a substrate support assembly used to support a semiconductor substrate in a semiconductor processing apparatus.

    Abstract translation: 摘要本文描述了一种用于检测用于在半导体处理装置中支撑半导体衬底的衬底支撑组件的多路复用多加热器区域加热板中的故障状况的方法。

    IMPROVED SUBSTRATE TEMPERATURE CONTROL BY USING LIQUID CONTROLLED MULTIZONE SUBSTRATE SUPPORT
    9.
    发明申请
    IMPROVED SUBSTRATE TEMPERATURE CONTROL BY USING LIQUID CONTROLLED MULTIZONE SUBSTRATE SUPPORT 审中-公开
    液体控制多区衬底支撑改善衬底温度控制

    公开(公告)号：WO2010055441A3

    公开(公告)日：2010-07-08

    申请号：PCT/IB2009054876

    申请日：2009-11-03

    Applicant: LAM RES CORP ,  LAM RES AG ,  SINGH HARMEET ,  COMENDANT KEITH

    Inventor： SINGH HARMEET ,  COMENDANT KEITH

    IPC: C23C14/50 ,  C23C16/46

    CPC classification number: H01L21/67248 ,  C23C16/4586 ,  C23C16/46 ,  C23C16/463 ,  C23C16/50 ,  C23C16/52 ,  H01J2237/2001 ,  H01L21/67109 ,  H01L21/6831

    Abstract: A substrate support useful in a reaction chamber of a plasma processing apparatus is provided. The substrate support comprises a base member and a heat transfer member overlying the base member. The heat transfer member has multiple zones to individually heat and cool each zone of the heat transfer member. An electrostatic chuck overlies the heat transfer member. The electrostatic chuck has a support surface for supporting a substrate in a reaction chamber of the plasma processing apparatus. A source of cold liquid and a source of hot liquid are in fluid communication with flow passages in each zone. A valve arrangement is operable to independently control temperature of the liquid by adjusting a mixing ratio of the hot liquid to the cold liquid circulating in the flow passages. In another embodiment, heating elements along a supply line and transfer lines heat a liquid from a liquid source before circulating in the flow passages.

    Abstract translation: 提供可用于等离子体处理设备的反应室中的衬底支撑件。 基板支撑件包括基座构件和覆盖基座构件的传热构件。 传热构件具有多个区域以分别加热和冷却传热构件的每个区域。 静电吸盘覆盖传热构件。 静电吸盘具有用于支撑等离子体处理设备的反应室中的基板的支撑表面。 冷液体源和热液体源与每个区域中的流动通道流体连通。 阀装置可操作以通过调节热流体与在流动通道中循环的冷流体的混合比来独立地控制液体的温度。 在另一个实施例中，沿供应管线和传输管线的加热元件在流动通道中循环之前加热来自液体源的液体。

    GAS INJECTION TO ETCH A SEMICONDUCTOR SUBSTRATE UNIFORMLY
    10.
    发明申请
    GAS INJECTION TO ETCH A SEMICONDUCTOR SUBSTRATE UNIFORMLY 审中-公开
    注入半导体衬底的气体注入均匀

    公开(公告)号：WO2007149210A3

    公开(公告)日：2008-02-07

    申请号：PCT/US2007013159

    申请日：2007-06-05

    Applicant: LAM RES CORP ,  SINGH HARMEET ,  COOPERBERG DAVID ,  VAHEDI VAHID

    Inventor： SINGH HARMEET ,  COOPERBERG DAVID ,  VAHEDI VAHID

    IPC: H01L21/02

    CPC classification number: H01L21/6708 ,  H01J37/321 ,  H01J37/3244 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/32137

    Abstract: A method of etching a semiconductor substrate with improved critical dimension uniformity comprises supporting a semiconductor substrate on a substrate support in an inductively coupled plasma etch chamber; supplying a first etch gas to a central region over the semiconductor substrate; supplying a second gas comprising at least one silicon containing gas to a peripheral region over the semiconductor substrate surrounding the central region, wherein a concentration of silicon in the second gas is greater than a concentration of silicon in the first etch gas; generating plasma from the first etch gas and second gas; and plasma etching an exposed surface of the semiconductor substrate.

    Abstract translation: 蚀刻具有改善的临界尺寸均匀性的半导体衬底的方法包括在电感耦合等离子体蚀刻室中的衬底支撑件上支撑半导体衬底; 向所述半导体衬底上的中心区域提供第一蚀刻气体; 将包含至少一种含硅气体的第二气体供应到围绕所述中心区域的所述半导体衬底上的周边区域，其中所述第二气体中的硅浓度大于所述第一蚀刻气体中的硅浓度; 从第一蚀刻气体和第二气体产生等离子体; 并且等离子体蚀刻半导体衬底的暴露表面。

Patent Agency Ranking