公开(公告)号：JP2001102451A

公开(公告)日：2001-04-13

申请号：JP2000242831

申请日：2000-08-10

Applicant: LUCENT TECHNOLOGIES INC

Inventor： ABDELGADIR MAHJOUB ALI ,  NEISU RAYADI ,  MERCHANT SAILESH MANSINH ,  BIBEKKU SAKUSENA ,  PAI H I

IPC: H01L21/3205 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit comprising a structure where an inter-line capacitance is reduced, and to provide a manufacturing method for an integrated circuit wherein an impurity is prevented from causing a destructive reaction with a conductive element present in the next layer of a multi-layer integrated circuit structure. SOLUTION: A cap layer or barrier layer which prevents an impurity from moving in a low permittivity material prevents the impurity from causing a destructive reaction with a conductive element present in the next layer of a multi-layer integrated circuit structure. Related to an integrated circuit, a diffusion preventive barrier layer is deposited between a first dielectrics layer and a conductive layer above the integrated circuit. The diffusion-preventive barrier layer is the next metal layer which is formed, on the spot, at the dielectrics layer comprising impurity, and further, a process including polishing is performed with a multi-layer dielectrics structure. The on-the-spot deposition at the cap layer or barrier layer prevents a layer comprising impurities from being exposed to an atmosphere, and the cap layer or barrier layer prevents the layer from being contaminated with water content, hydrogen, etc.

公开(公告)号：JP2001118928A

公开(公告)日：2001-04-27

申请号：JP2000246203

申请日：2000-08-15

Applicant: LUCENT TECHNOLOGIES INC

Inventor： ALVARO MAURY ,  ABDELGADIR MAHJOUB ALI

IPC: H01L23/522 ,  C23C14/08 ,  C23C14/58 ,  H01L21/02 ,  H01L21/28 ,  H01L21/304 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532 ,  H01L29/51

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a flat inter-level dielectric layer of low k, which comprises an FSG layer of HDP-CVD which protects a conductive layer from fluorine. SOLUTION: A method is comprised where a conductive layer is deposited near a semiconductor substrate, and the conductive layer is formed multiple stages, in which a plurality of conductive lines comprising gap are formed. The conductive layer is a metal layer which comprises at least either aluminum or copper. An FSG layer is formed on the conductive layer which is patterned by a high density plasma CVD, filling the gap between conductor lines. Furthermore, a method is comprised where the FSG layer is chemically-mechanically polished, and an undoped oxide layer is deposited over the FSG layer. The peak of FSG layer, corresponding to the width of a conductive metal line, is reduced by a step of CMP. Thus, a following conductive layers that follow are protected from being exposed to fluorine due to the FSG layer.

公开(公告)号：JP2001053142A

公开(公告)日：2001-02-23

申请号：JP2000199726

申请日：2000-06-30

Applicant: LUCENT TECHNOLOGIES INC

Inventor： ABDELGADIR MAHJOUB ALI ,  GIBSON JR GERALD W ,  GUNTER STEVEN GREGORY ,  MAURY ALVARO

IPC: H01L21/76 ,  H01L21/308

Abstract: PROBLEM TO BE SOLVED: To form a planarized shallow trench insulation region, without the use of chemical and mechanical polishing by removing a part of an insulation layer formed on a material layer to expose a part of a trench insulation layer, and then removing the insulation layer on the material layer using a life-off process. SOLUTION: A pad oxide layer 105 is formed between a material layer 110 and a substrate 100, and after a trench is formed by etching, an insulation layer 130 is formed on the material layer 110 and in the trench. The material and deposition process of the insulation layer 130 are selected to form a thin region 135. When the material layer 110 of SiN is etched, using hot phosphoric acid after a region 125 of the material layer 110 is exposed by removing the thin region 135, an insulation region 140 above the pad oxide has a step height in the range of 200-1,000 Å and the insulation region 140 has an overall thickness X5 in the range of 3,500-4,000 Å. According to the method, a planarized shallow trench insulation region can be formed, without using chemical and mechanical polishing.

公开(公告)号：JP2001118843A

公开(公告)日：2001-04-27

申请号：JP2000242829

申请日：2000-08-10

Applicant: LUCENT TECHNOLOGIES INC

Inventor： ABDELGADIR MAHJOUB ALI ,  BIBEKKU SAKUSENA

IPC: C23C16/30 ,  C23C16/40 ,  H01L21/205 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide an extra large-scale integrated circuit having a high aspect ratio function by using a technology for forming low-k dielectric ILDs having such an integrated circuit structure that avoids the harmful trend of high density plasma enhanced CVD (HDP-CVD) and, at the same time, reduces the occurrence of voids; a process for depositing a low-k dielectric material in the extra large- scale integrated circuit; and an integrated circuit manufactured by using the process. SOLUTION: An integrated circuit manufacturing technology by which a protective layer is deposited on the conductive elements of a specific layer in a multilayered integrated circuit is disclosed. A low-k dielectric layer is deposited on a protective film forming material layer by, preferably, HDP-CVD. The disclosed process fills up the gap of =3). By means of the fluorine embodied in the embodiment, the interline capacitance CL-L of the low-k dielectric film is reduced by 10% as compared with the conventional non-doped dielectric material.

公开(公告)号：JP2000223573A

公开(公告)日：2000-08-11

申请号：JP2000016665

申请日：2000-01-26

Applicant: LUCENT TECHNOLOGIES INC

Inventor： ABDELGADIR MAHJOUB ALI ,  ALVARO MAURY

IPC: H01L27/10 ,  C23C14/08 ,  C23C14/58 ,  H01L21/02 ,  H01L21/28 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/51

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit element, having a planarized inter- level dielectric layer with a low permittivity (K) containing an FSG layer of which conductive layer is protected from exposure to fluorine. SOLUTION: This integrated circuit 28 contains a conductive layer adjacent to a semiconductor substrate 30. The conductive layer contains conductive wires having gaps therebetween. A fluorine-silicate glass(FSG) layer covers a patterned conductive layer and fills the gaps between the conductive wires. An undoped oxide layer 38 exists on an FSG layer 36. The peak of the FSG layer 36 covering the conductive metal wires is reduced through CMP. Thus, the FSG film 36 of the following conductive layer is substantially protected from exposure to fluorine.

公开(公告)号：GB2359661B

公开(公告)日：2002-11-20

申请号：GB0019483

申请日：2000-08-08

Applicant: LUCENT TECHNOLOGIES INC

Inventor： ABDELGADIR MAHJOUB ALI ,  LAYADI NACE ,  MERCHANT SAILESH MANSINH ,  SAXENA VIVEK ,  YIH PEI H

IPC: H01L21/3205 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A cap or barrier layer that can prevent the migration of impurities in low dielectric constant material, thereby preventing the impurities from attacking conductive elements in subsequent levels of a multi-level integrated circuit structure. The integrated circuit by may be fabricated by disposing the diffusion-preventing barrier layer between a first dielectric layer and the conductive layer at an upper level of the integrated circuit. The diffusion preventing barrier layer may be formed in-situ over the impurity containing dielectric material with the subsequent disposition of a metal layer thereover, and further processing of a multi-layer dielectric structure to include polishing. The in-situ deposition of the cap or barrier layer prevents the exposure of the impurity containing layer to atmosphere, thereby avoiding contamination of the layer by moisture absorption, hydrogen absorption, or the like. In an exemplary embodiment, the diffusion preventing barrier layer is a material containing silicon oxide or silicon rich silicon oxide SiOx, where x is preferably less than 2.

公开(公告)号：GB2359661A

公开(公告)日：2001-08-29

申请号：GB0019483

申请日：2000-08-08

Applicant: LUCENT TECHNOLOGIES INC

Inventor： ABDELGADIR MAHJOUB ALI ,  LAYADI NACE ,  MERCHANT SAILESH MANSINH ,  SAXENA VIVEK ,  YIH PEI H

IPC: H01L21/3205 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A cap or barrier that can prevent the migration of impurities in low dielectric constant material, thereby preventing the impurities from attacking conductive elements in subsequent levels of a multi-level integrated circuit structure. The integrated circuit may be fabricated by disposing the diffusion-preventing barrier layer (104) between a first dielectric layer (103) and the conductive layer (201) at an upper level of the integrated circuit. The diffusion preventing barrier layer may be formed in-situ over the impurity containing dielectric material with the subsequent disposition of a metal layer thereover, and further processing of a multi-layer dielectric structure to include polishing. The in-situ deposition of the cap or barrier layer prevents the exposure of the impurity containing layer to atmosphere, thereby avoiding contamination of the layer by moisture absorption, hydrogen absorption, or the like. In an exemplary embodiment, the diffusion preventing barrier layer is a material containing silicon oxide or silicon rich silicon oxide SiO x , where x is preferably less than 2 and the first dielectric layer is fluorosilicate glass (FSG).

公开(公告)号：GB2352874A

公开(公告)日：2001-02-07

申请号：GB0014544

申请日：2000-06-14

Applicant: LUCENT TECHNOLOGIES INC

Inventor： ABDELGADIR MAHJOUB ALI ,  GIBSON JR GERALD W ,  GUNTER STEVEN GREGORY ,  MAURY ALVARO

IPC: H01L21/762

Abstract: A method of manufacturing an integrated circuit including shallow trench isolation (STI) regions includes providing substrate (100) with material layer (110) and trenches (115, Fig. 5). Insulating layer (130) is formed over material layer (110) and in the trenches. A portion of the insulating layer is removed to expose trenched isolation layer (125). The insulating layer formed above the material layer is then removed using a lift-off method to complete the shallow trench isolation regions (140, Fig. 8). Planarised STI regions can therefore be performed without using chemical mechanical polishing (CMP). A hardmask may be used instead of material layer (110). A partially formed integrated circuit with substrate (100), hardmask and insulating layer (130) is also disclosed, where insulating layer (130) is formed in a trench and above the hardmask and an area of the hardmask adjacent to the trench is not covered by the insulating layer (130).

公开(公告)号：GB2352874B

公开(公告)日：2002-10-09

申请号：GB0014544

申请日：2000-06-14

Applicant: LUCENT TECHNOLOGIES INC

Inventor： ABDELGADIR MAHJOUB ALI ,  GIBSON JR GERALD W ,  GUNTER STEVEN GREGORY ,  MAURY ALVARO

IPC: H01L21/762

公开(公告)号：GB2356289A

公开(公告)日：2001-05-16

申请号：GB0019486

申请日：2000-08-08

Applicant: LUCENT TECHNOLOGIES INC

Inventor： ABDELGADIR MAHJOUB ALI ,  SAXENA VIVEK

IPC: C23C16/40 ,  H01L21/205 ,  C23C16/30 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A technique for fabricating an integrated circuit in which a protective layer 303 of undoped silicon glass (USG) is deposited over conductive elements 302 . A layer of low-k dielectric material 304 such as fluorosilicate glass (FSG) is deposited over the protective layer 303 , preferably by high density plasma chemical vapour deposition (HDP-CVD). The process results in significantly improved gap fill capabilities for high aspect ratio conductive features (aspect ratio of order of two or more) with spacing between the features of less than 300nm. By virtue of the fluorine incorporation in the exemplary embodiment, a reduction of the order of 10% in line-to-line capacitance, C L-L , may be realised when compared to conventional undoped dielectric materials.