公开(公告)号：JP2001053142A

公开(公告)日：2001-02-23

申请号：JP2000199726

申请日：2000-06-30

Applicant: LUCENT TECHNOLOGIES INC

Inventor： ABDELGADIR MAHJOUB ALI ,  GIBSON JR GERALD W ,  GUNTER STEVEN GREGORY ,  MAURY ALVARO

IPC: H01L21/76 ,  H01L21/308

Abstract: PROBLEM TO BE SOLVED: To form a planarized shallow trench insulation region, without the use of chemical and mechanical polishing by removing a part of an insulation layer formed on a material layer to expose a part of a trench insulation layer, and then removing the insulation layer on the material layer using a life-off process. SOLUTION: A pad oxide layer 105 is formed between a material layer 110 and a substrate 100, and after a trench is formed by etching, an insulation layer 130 is formed on the material layer 110 and in the trench. The material and deposition process of the insulation layer 130 are selected to form a thin region 135. When the material layer 110 of SiN is etched, using hot phosphoric acid after a region 125 of the material layer 110 is exposed by removing the thin region 135, an insulation region 140 above the pad oxide has a step height in the range of 200-1,000 Å and the insulation region 140 has an overall thickness X5 in the range of 3,500-4,000 Å. According to the method, a planarized shallow trench insulation region can be formed, without using chemical and mechanical polishing.

公开(公告)号：GB2352874B

公开(公告)日：2002-10-09

申请号：GB0014544

申请日：2000-06-14

Applicant: LUCENT TECHNOLOGIES INC

Inventor： ABDELGADIR MAHJOUB ALI ,  GIBSON JR GERALD W ,  GUNTER STEVEN GREGORY ,  MAURY ALVARO

IPC: H01L21/762

公开(公告)号：GB2358734A

公开(公告)日：2001-08-01

申请号：GB0019969

申请日：2000-08-14

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GIBSON JR GERALD W ,  LYTLE STEVEN ALAN ,  ROBY MARY DRUMMOND ,  VITKAVAGE DANIEL JOSEPH ,  WOLF THOMAS MICHAEL

IPC: H01L27/00 ,  H01L21/316 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L23/532 ,  H01L27/04

Abstract: A process for fabricating integrated circuit comprising dielectric structural layer (101) and low dielectric constant (low-k) layer (102) disposed over substrate (100) is disclosed. The low k-layer (102) may exist between conductive elements (103) such as vias and trenches in a dual-damascene structure. The low-k layer (102) may have a dielectric constant below 3.7 and be composed of organic polymers including hybrido organo siloxane polymers, nanoporous silicate glass or organo silicate glass. The structural layer (101) may be composed of silicon dioxide (SiO 2 ) or fluorine doped silicon dioxide (FSG), and have a Young's modulus between 60 and 120 GPa. The low k-layer (102) reduces the overall dielectric constant in the structure and the intralayer or line-to-line capacitance between conductive elements (103). A via may exist in the structural layer, or the structural layer may be disposed directly on a conductive layer.

公开(公告)号：GB2358733A

公开(公告)日：2001-08-01

申请号：GB0019968

申请日：2000-08-14

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GIBSON JR GERALD W ,  LYTLE STEVEN ALAN ,  ROBY MARY DRUMMOND ,  VITKAVAGE DANIEL JOSEPH ,  WOLF THOMAS MICHAEL

IPC: H01L21/768 ,  H01L21/314 ,  H01L21/316 ,  H01L23/522 ,  H01L23/532 ,  H01L27/00

Abstract: An integrated circuit comprises dielectric structural layer (101) and low dielectric constant (low-k) layer (102) disposed over substrate (100). The low k-layer (102) may exist between conductive elements (103) such as vias and trenches in a dual-damascene structure. The low-k layer (102) may have a dielectric constant below 3.7 and be composed of organic polymers including hybrido organo siloxane polymers, nanoporous silicate glass or organo silicate glass. The structural layer (101) may be composed of silicon dioxide (SiO 2 ) or fluorine doped silicon dioxide (FSG), and have a Young's modulus between 60 and 120 GPa. The low k-layer (102) reduces the overall dielectric constant in the structure and the intralayer or line-to-line capacitance between conductive elements (103). A via may exist in the structural layer, or the structural layer may be disposed directly on a conductive layer.

公开(公告)号：GB2352874A

公开(公告)日：2001-02-07

申请号：GB0014544

申请日：2000-06-14

Applicant: LUCENT TECHNOLOGIES INC

Inventor： ABDELGADIR MAHJOUB ALI ,  GIBSON JR GERALD W ,  GUNTER STEVEN GREGORY ,  MAURY ALVARO

IPC: H01L21/762

Abstract: A method of manufacturing an integrated circuit including shallow trench isolation (STI) regions includes providing substrate (100) with material layer (110) and trenches (115, Fig. 5). Insulating layer (130) is formed over material layer (110) and in the trenches. A portion of the insulating layer is removed to expose trenched isolation layer (125). The insulating layer formed above the material layer is then removed using a lift-off method to complete the shallow trench isolation regions (140, Fig. 8). Planarised STI regions can therefore be performed without using chemical mechanical polishing (CMP). A hardmask may be used instead of material layer (110). A partially formed integrated circuit with substrate (100), hardmask and insulating layer (130) is also disclosed, where insulating layer (130) is formed in a trench and above the hardmask and an area of the hardmask adjacent to the trench is not covered by the insulating layer (130).