公开(公告)号：JP2001102451A

公开(公告)日：2001-04-13

申请号：JP2000242831

申请日：2000-08-10

Applicant: LUCENT TECHNOLOGIES INC

Inventor： ABDELGADIR MAHJOUB ALI ,  NEISU RAYADI ,  MERCHANT SAILESH MANSINH ,  BIBEKKU SAKUSENA ,  PAI H I

IPC: H01L21/3205 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit comprising a structure where an inter-line capacitance is reduced, and to provide a manufacturing method for an integrated circuit wherein an impurity is prevented from causing a destructive reaction with a conductive element present in the next layer of a multi-layer integrated circuit structure. SOLUTION: A cap layer or barrier layer which prevents an impurity from moving in a low permittivity material prevents the impurity from causing a destructive reaction with a conductive element present in the next layer of a multi-layer integrated circuit structure. Related to an integrated circuit, a diffusion preventive barrier layer is deposited between a first dielectrics layer and a conductive layer above the integrated circuit. The diffusion-preventive barrier layer is the next metal layer which is formed, on the spot, at the dielectrics layer comprising impurity, and further, a process including polishing is performed with a multi-layer dielectrics structure. The on-the-spot deposition at the cap layer or barrier layer prevents a layer comprising impurities from being exposed to an atmosphere, and the cap layer or barrier layer prevents the layer from being contaminated with water content, hydrogen, etc.

公开(公告)号：JP2001217187A

公开(公告)日：2001-08-10

申请号：JP2000372411

申请日：2000-12-07

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DAVID MAKUERUROI BOURIN ,  FARROW REGINALD CONWAY ,  KIZILYALLI ISIK C ,  NEISU RAYADI ,  MKRTCHYAN MASIS

IPC: G03F7/20 ,  G03F9/00 ,  H01J37/304 ,  H01J37/305 ,  H01L21/027 ,  H01L23/544

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming an alignment feature and for connecting it to a SCALPEL tool in or on a multilayer semiconductor structure for the purpose of alignment with a lithography mask. SOLUTION: This method is to form a multilayer semiconductor structure equipped with an alignment feature for alignment with a lithography mask or for use with a SCALPEL tool. This invention is suitable particularly for a submicron CMOS technology device and circuit, but is not limited to them. This invention is useful because of the use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer, and further useful become of an alignment feature in an earlier stage (that is, zero level) of a semiconductor device manufacturing process.

公开(公告)号：JP2001358065A

公开(公告)日：2001-12-26

申请号：JP2001111006

申请日：2001-04-10

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DAVID MAKUERUROI BOURIN ,  FARROW REGINALD CONWAY ,  KIZILYALLI ISIK C ,  NEISU RAYADI ,  MKRTCHYAN MASIS

IPC: G03F7/20 ,  G03F9/00 ,  H01J37/304 ,  H01J37/305 ,  H01L21/027 ,  H01L23/544

Abstract: PROBLEM TO BE SOLVED: To provide a method capable of using by forming an alignment feature in a multilayer semiconductor structure or on the multilayer semiconductor structure and connecting the feature to an SCALPEL tool. SOLUTION: A method for forming a multilayer semiconductor structure has the alignment feature to match a lithography mask and capable of using together with the SCALPEL tool. The method is particularly suitable for submicron CMOS technical device and circuit, but not limited only to them. The method is advantageous since the method can use an electron beam source in both matching and exposing the lithography mask on a semiconductor wafer. The method is advantageous since the alignment feature can be formed at an early stage (that is, a zero level) in a step of manufacturing a semiconductor device.

公开(公告)号：JP2001196455A

公开(公告)日：2001-07-19

申请号：JP2000328233

申请日：2000-10-27

Applicant: LUCENT TECHNOLOGIES INC

Inventor： NEISU RAYADI ,  MERCHANT SAILESH M ,  MOLLOY SIMON JOHN ,  ROY PRADIP K

IPC: H01L21/302 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To reduce the number of processing steps when manufacturing a semiconductor element having a via, which is formed through a material having a low permittivity. SOLUTION: A first conductive layer is formed near the substrate, an etching stopping layer is formed on the first conductive layer, and a dielectric layer is formed on the etching stopping layer. The dielectric layer contains a material having a low permittivity, a via is formed through the dielectric layer to expose the etching stopping layer at the bottom, and a perforated sidewall is formed. At the same time, an etching agent is used which acts together with a material etched from the etching stopping layer. Thus, a polymeric layer covering the sidewall having holes of the via is formed to reduce the steps. On a rear sidewall having a polymeric material etched from the bottom of the via, a barrier metallic layer is formed on the polymeric layer. Further, a seed layer is formed on the barrier metallic layer, and a second conductive layer making contact with the first conductive layer in the via is formed on the seed layer.

公开(公告)号：JP2001053247A

公开(公告)日：2001-02-23

申请号：JP2000228309

申请日：2000-07-28

Applicant: LUCENT TECHNOLOGIES INC

Inventor： CHAUDHRY SAMIR ,  CHETLUR SUNDAR SRINIVASAN ,  NEISU RAYADI ,  ROY PRADIP KUMAR ,  VAIDYA HEM M

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To provide the manufacturing method of a capacitor, which increases the capacity of the capacitor without reducing reliability of the capacitor. SOLUTION: This manufacturing method of this capacitor has a step of form an interconnection line 26 over a substrate 24, a step of depositing a first dielectric layer 28 on the line 26, a step of etching a through hole (increases toward the direction of the substrate and has a width of a tapered form) in the layer 28, a step of filling a conductive metal layer in the through hole for forming a metallic plug 32 in the layer 28, a step of etching a trench 30 in the layer 28 on the periphery of the upper part of the plug 32, a step of deposing a second dielectric layer 38 on a lower electric layer 36, in close proximity to the plug 32 and a step to deposit an upper electrode layer 40 on the layer 28.

公开(公告)号：JP2000208730A

公开(公告)日：2000-07-28

申请号：JP2000004299

申请日：2000-01-13

Applicant: LUCENT TECHNOLOGIES INC

Inventor： SAMIA CHAADORII ,  SANDER SRINIVASAN CHETTLER ,  NEISU RAYADI ,  ROY PRADIP K ,  HEMU M VAIDEA

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a capacity of an integrated circuit including a plug having a gradient. SOLUTION: The capacity of an integrated circuit contains a first dielectric substance layer 42 which is arranged adjacent to a substrate 24 and is provided with a groove therein and a metallic plug 32, which includes an upper part extending upward in the groove and a lower part arranged in the first dielectric substance layer 42. The lower part has a width having gradient increasing in the direction of the substrate, thereby fixing the metallic plug 32 in the dielectric substance layer 42. The upper part is preferably provided having a gradient as well. Furthermore, a second dielectric substance layer 38 is adjacent to the metallic plug 32 and is provided with an upper electrode 40 thereon.