公开(公告)号：JP2001201534A

公开(公告)日：2001-07-27

申请号：JP2000340172

申请日：2000-11-08

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON

IPC: G01R31/26 ,  H01L21/60 ,  H01L21/607 ,  H01L21/66 ,  H01L23/485

Abstract: PROBLEM TO BE SOLVED: To provide an IC test method for an IC die having a wire, a bond, and a pad. SOLUTION: The specifications mention a technique of putting an IC die to the burn-in electric test before wire-bonding of the IC die to the next mutual connection level. The die is provided with a soldering bump array for testing. The array is mutually connected to an IC contact pad of the die. A KGD(Known Good Dies) is wire bonded in a next interconnection level or flip chip soldering bump bonded.

公开(公告)号：JP2000243777A

公开(公告)日：2000-09-08

申请号：JP2000044330

申请日：2000-02-22

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON ,  KOSSIVES DEAN PAUL

IPC: H05K3/34 ,  H01L21/60 ,  H01L23/485

Abstract: PROBLEM TO BE SOLVED: To obtain a method for bonding an IC chip to a support substrate, in which a solder bump can be formed at an aluminum bonding position. SOLUTION: In order to form a solder bump at a bonding position of Al, under bump metal(UBM) layers 21, 22, 23 are formed at first at a solder bump position. A cap layer 14 on an IC chip is coated with photoresist and patterned, to expose an UBM and the peripheral part of the cap layer around the UBM. Subsequently, solder paste 62 is applied and subjected to reflow, thus forming a solder bump 71. Since solidified photoresist is difficult to remove after reflow step, a sacrificial buffer layer 21 is provided between a photoresist mask 51 and the cap layer 14, thus facilitating removal of a photoresist 51.

公开(公告)号：JP2000049248A

公开(公告)日：2000-02-18

申请号：JP20518199

申请日：1999-07-19

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON ,  FRYE ROBERT CHARLES ,  II REN ROO

IPC: H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H05K1/18

Abstract: PROBLEM TO BE SOLVED: To provide an IC package where interconnection density can be improved. SOLUTION: A storage chip IC package has edge connectors 31 and 32, which extend to a base from the upper face of PWB14 along the edge and the sidewall of a cavity 15 for storing an IC chip 11, which is installed in a printed circuit board (PWB) 14. The edge connectors 31 and 32 operate as interconnection parts, instead of through-hole interconnection parts, and they improve mutual connection density. When the edge connectors 31 and 32 are used as interconnection parts for power and interconnection parts for ground, a signal I/O pad and a signal runner are insulated effectively.

公开(公告)号：JPH11317418A

公开(公告)日：1999-11-16

申请号：JP5311699

申请日：1999-03-01

Applicant: LUCENT TECHNOLOGIES INC

Inventor： AHLQUIST LOUIS NELSON ,  DEGANI YINON

IPC: H01L21/48 ,  H01L21/60

Abstract: PROBLEM TO BE SOLVED: To dimensionally stabilize a pattern by forming crosslinking with actinic radiation, after patterning a photoresist used for a lift-off process by the lithographic method before performing high-temperature treatment. SOLUTION: A photoresist material left after patterning a window is exposed to a large quantity of radiation. A wafer subjected to lithographic irradiation is set up in a sputtering device and an under-bump metallized(UBM) layer 31 is deposited on the wafer. A preferable UBM layer 31 has a multilayered structure composed of Cr and Cu. However, this is just one of the various kinds of UBM materials. A Cr-Cr/Cu-Cu composite structure is formed by successively depositing a plurality of layers for forming the UBM layer 31. The composite UBM layer 31 is deposited on a photoresist layer 26 on a pad 24 for contact exposed by the window. Therefore, the unwanted portion of the layer 31 is removed by dissolving the photoresist of the photoresist layer 26 in a photoresist solvent by using the lift-off technique.

公开(公告)号：JPH1187549A

公开(公告)日：1999-03-30

申请号：JP20241898

申请日：1998-07-17

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON ,  SMITH PETER R ,  TAI KING L

IPC: H01L23/02 ,  H01L23/00 ,  H01L23/04 ,  H01L23/12 ,  H01L23/538 ,  H01L23/66 ,  H01L25/04 ,  H01L25/065 ,  H01L25/18

Abstract: PROBLEM TO BE SOLVED: To lessen grounding connections in length and impedance by a method wherein the grounding interconnections of an RF chip is provided direct between the chip and an SPWB. SOLUTION: Grounding connections are formed between an RF chip 11 and the common grounding plane 21 of an SPWB 18. The backside of the RF chip 11 is coated with a metal coating layer 32 of Au or the like. Then, the RF chip 11 coated with metal is connected direct to a grounding plane pad 34 with a conductive material 33. The grounding plane pad 34 is a part of the common grounding plane 21 of the SPWB. Therefore, an RF semiconductor chip can be connected direct to an SPWB connecting pad without additionally coating a chip board 13 with metal. In nearly all cases, when a semiconductor substrate is coated with metal, a grounding connection is lessened in resistance. Furthermore, a metal coating usually improves the semiconductor substrate in adhesion and promotes an effective connection.

公开(公告)号：JPH09186289A

公开(公告)日：1997-07-15

申请号：JP32826096

申请日：1996-12-09

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON ,  HAN BYUNG JOON ,  DUDDERAR THOMAS DIXON

IPC: H01L25/18 ,  H01L25/065 ,  H01L25/07

Abstract: PROBLEM TO BE SOLVED: To provide the assembly of integrated circuit chips laminated in multilayers. SOLUTION: The chip assembly of the laminated structure of multilayers is constituted by alternately disposing chips 11, 12, 13, 14, 15, 16, 17, 18 and connecting layers 122, 142, 162, 182 and solder bumps 201. The advantage is that the bottom surface of the chip is connected to the upper surface of the chip by insulating connecting layer. Further, another advantage is that the wiring pad on the bottom surface of the flip-chip is electrically connected to the wiring pad of the chip on the upper surface of the next lower level by the solder bump.

公开(公告)号：JP2002043461A

公开(公告)日：2002-02-08

申请号：JP2000199728

申请日：2000-06-30

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON ,  DUDDERAR THOMAS D ,  FRYE ROBERT CHARLES

IPC: H05K3/34 ,  H01L23/12 ,  H01L23/32

Abstract: PROBLEM TO BE SOLVED: To provide an IC package having a high-density I/O wherein an IC chip is bonded to a silicon intermediate interconnect substrate (IIS) and the IIS is wire-bonded to a printed wiring board(PWB). SOLUTION: This package comprises the PWB having wire-bonding pads on its upper surface, the semiconductor IIS, a means for die-bonding the lower surface of the IIS to the upper surface of the PWB, and a means for wire- bonding the wire-bonding pads on the IIS to the wire-bonding pad on the PWB. Further, the IIS comprises a semiconductor substrate having a center region on its upper surface, IIS interconnect sites on the center region of the upper surface of the semiconductor substrate, the IIS wire-bonding pads around the center region of the upper surface of the semiconductor substrate, and a metallized runner which interconnects the IIS interconnect sites with the IIS wire- bonding pads.

公开(公告)号：JP2000124265A

公开(公告)日：2000-04-28

申请号：JP28984099

申请日：1999-10-12

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON ,  JEFFREY ALAN GREGGS

IPC: H05K3/34 ,  H01L21/60 ,  H01L23/485

Abstract: PROBLEM TO BE SOLVED: To obtain a new material which is used for an underbump metallization(UBM) coating by a method wherein a pure aluminum surface is formed on an aluminum bonding part, a copper layer is formed on the pure aluminum surface and the copper layer is soldered to a support substrate. SOLUTION: An oxide layer 52 is formed on an IC substrate 51. A cap layer 53 is formed on the oxide layer 52. In addition, an aluminum bonding layer 54 is formed on the cap layer 53. Then, before a UBM layer is formed on such an IC chip, the surface of the aluminum bonding part 54 is cleaned by using a mild etching operation, or it is cleaned by a backsputtering operation. After that, an underbump aluminum layer 55 as a pure aluminum surface is formed. The aluminum layer 55 is sputtered directly, and a copper layer 56 is deposited. As a result, it is possible to obtain a new material which can be used for a UBM coating.

公开(公告)号：JPH11337615A

公开(公告)日：1999-12-10

申请号：JP35496198

申请日：1998-12-14

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON ,  LYONS ALAN M

IPC: G01R31/26 ,  G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  H05K3/32

Abstract: PROBLEM TO BE SOLVED: To obtain an electrical test method, in which a test procedure is simplified and the reliability of the test procedure can be improved by a method, wherein an IC package is mounted by using an anisotropic conductor, on an interconnection board for test. SOLUTION: An interconnection board 11, for test, which is provided with pads 12 for contact is covered with an adhesive anisotropic conductor 13 in the interface between an electric contact row and an adhesive layer by the anisotropic conductor 13. An IC device 14, which is provided with solder bump contacts 15, is bonded and arranged in a state such that the pads 12 for contact and the solder bump contacts 15 are aligned. The anisotropic conductor 13 contains normally spherical conductive particles 17 which are contained inside a polymer matrix. A pressure which is applied to the anisotropic conductor 13 is indicated by arrows 18, and the conductive particles 17 are trapped between contact surfaces so as to form a conductive path in the Z-axis direction.

公开(公告)号：JP2001244406A

公开(公告)日：2001-09-07

申请号：JP2001026208

申请日：2001-02-02

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON ,  DUDDERAR THOMAS D ,  TAI KING L

IPC: H01L23/12 ,  H01L23/36 ,  H01L23/50 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34

Abstract: PROBLEM TO BE SOLVED: To provide a multi-chip IC package with high interconnection density. SOLUTION: The upper surface (or lower surface) of a flexible substrate is joined to a rigid support substrate with an opening for accommodating an IC chip that is joined to the upper surface (or lower surface) of the flexible substrate. In a preferred embodiment, a plurality of IC memories are mounted to one surface of the flexible substrate, and at least one logic chip is mounted to the other surface. An extremely thin flexible substrate is used to optimize the through hole interconnection length between the memory element and the logic element. When the logic chip is to be mounted to a hollow part that is formed by an opening by flip chips, a heat sink plate is used to cover the hollow part and at the same time perform efficient thermal contact to the reverse side of the logic chip.