公开(公告)号：JP2002043461A

公开(公告)日：2002-02-08

申请号：JP2000199728

申请日：2000-06-30

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON ,  DUDDERAR THOMAS D ,  FRYE ROBERT CHARLES

IPC: H05K3/34 ,  H01L23/12 ,  H01L23/32

Abstract: PROBLEM TO BE SOLVED: To provide an IC package having a high-density I/O wherein an IC chip is bonded to a silicon intermediate interconnect substrate (IIS) and the IIS is wire-bonded to a printed wiring board(PWB). SOLUTION: This package comprises the PWB having wire-bonding pads on its upper surface, the semiconductor IIS, a means for die-bonding the lower surface of the IIS to the upper surface of the PWB, and a means for wire- bonding the wire-bonding pads on the IIS to the wire-bonding pad on the PWB. Further, the IIS comprises a semiconductor substrate having a center region on its upper surface, IIS interconnect sites on the center region of the upper surface of the semiconductor substrate, the IIS wire-bonding pads around the center region of the upper surface of the semiconductor substrate, and a metallized runner which interconnects the IIS interconnect sites with the IIS wire- bonding pads.

公开(公告)号：JPH11195746A

公开(公告)日：1999-07-21

申请号：JP28571498

申请日：1998-10-07

Applicant: LUCENT TECHNOLOGIES INC

Inventor： FRYE ROBERT CHARLES ,  LOW YEE LENG ,  O'CONNOR KEVIN JOHN

IPC: H01L25/18 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07

Abstract: PROBLEM TO BE SOLVED: To assemble an inexpensive multi-level mutual connection with a simple structure by shifting at lest a part of an inter-chip mutual connecting circuit to a more smaller upper chip and including a runner on the other upper chip in the mutual connection to one of the upper chips. SOLUTION: A metal layer at a certain level is formed on a support chip. An upper chip 41 has a contact-point pad 62. A mutual connecting circuit at the single level is indicated by runners 63-65. An upper chip 67 undergoes flip- chip connection to a support-chip substrate 61 with solder bumps 68 and 69. An under-bump metablized layer 71 is ranged between the solder bump and the chip surface. In the metallic mutually connecting structure at the single level, runners 72-74 are formed on the upper chip 67. The runner 73 on the surface of the upper chip crosses the runner 64 on the surface of the support chip supported by the solder bumps 68 and 69. This cross-over is insulated with air by a gap 75.

公开(公告)号：JP2000261219A

公开(公告)日：2000-09-22

申请号：JP2000056110

申请日：2000-03-01

Applicant: LUCENT TECHNOLOGIES INC

Inventor： FRYE ROBERT CHARLES ,  II REN ROO ,  TAI KING LIEN

IPC: H01P3/08 ,  H01P11/00 ,  H05K3/24

Abstract: PROBLEM TO BE SOLVED: To realize a method for improving sharpness of the edge of a conductive metal strip formed by thick film paste technique. SOLUTION: This method produces a hybrid thick film in order to produce a metallic strip line. For the purpose of obtaining a minute shape of the strip, a trim strip 42 of a thin film is formed so as to cover the end part of a thick film strip 17. Though electric characteristics of this line are mainly prescribed by bulk characteristics of materials of the thick film 17, the shape of the like is prescribed by the thin film trim strip.

公开(公告)号：JP2000091462A

公开(公告)日：2000-03-31

申请号：JP25301799

申请日：1999-09-07

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON ,  DUDDERAR THOMAS D ,  FRYE ROBERT CHARLES ,  TAI KING L

IPC: H01L23/12 ,  H01L23/13 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To mutually wire one IC chip with a translator and obtain high mutual wiring density by a power source and an installation mutual wiring structure, using a power source step and a grounding step made in an isolated multistep structure mutual wiring translator. SOLUTION: A power source and a grounding step are provided with several- step isolated mutual wiring steps 31 to 34 on a translator 21 which is silicon. By a multistep structure mutual wiring feature included in the translator 21, several power source and grounding mutual wiring are adjusted and integrated by this board step. Then, a power source input/output or a grounding input/ output is further coupled to a next board step. Moreover, since the translator 21 accommodates a single multipin IC chip, it is made larger than the IC chip. This large translator region enables leading a pattern and developing it in all direction on the translator 21 made of silicon.

公开(公告)号：JP2003110087A

公开(公告)日：2003-04-11

申请号：JP2002231207

申请日：2002-08-08

Applicant: LUCENT TECHNOLOGIES INC

Inventor： FRYE ROBERT CHARLES ,  LOW YEE LENG ,  O'CONNOR KEVIN JOHN

IPC: H01L25/18 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07

Abstract: PROBLEM TO BE SOLVED: To provide a multilevel mutual connection assembly of low cost whose structure is simple. SOLUTION: At least a part of an interchip mutual connection circuit is shifted to a smaller (upper part) chip. When a plurality of upper part chips exist, an interchip circuit is designed as if mutual connection circuits on two chips contain a common mutual connection level, i.e., in such a manner that mutual connection to one chip out of upper chips contains a runner on another upper chip. The feature of constitution of this invention is that a gap which has been existed in chip-on-chip bonding is used for providing air insulation type crossover connection.

公开(公告)号：JP2000049248A

公开(公告)日：2000-02-18

申请号：JP20518199

申请日：1999-07-19

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON ,  FRYE ROBERT CHARLES ,  II REN ROO

IPC: H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H05K1/18

Abstract: PROBLEM TO BE SOLVED: To provide an IC package where interconnection density can be improved. SOLUTION: A storage chip IC package has edge connectors 31 and 32, which extend to a base from the upper face of PWB14 along the edge and the sidewall of a cavity 15 for storing an IC chip 11, which is installed in a printed circuit board (PWB) 14. The edge connectors 31 and 32 operate as interconnection parts, instead of through-hole interconnection parts, and they improve mutual connection density. When the edge connectors 31 and 32 are used as interconnection parts for power and interconnection parts for ground, a signal I/O pad and a signal runner are insulated effectively.

公开(公告)号：DE60018121D1

公开(公告)日：2005-03-24

申请号：DE60018121

申请日：2000-02-28

Applicant: LUCENT TECHNOLOGIES INC

Inventor： FRYE ROBERT CHARLES ,  LOW YEE LENG ,  TAI KING LIEN

IPC: H01P11/00 ,  H05K3/24 ,  H01P3/08

Abstract: The specification describes a method for improving the edge acuity of conductive metal strips formed by thick film paste techniques. The advantages of the bulk properties of strips formed using thick film technology are realized while the drawback of poor edge definition is overcome using a thin film trim strip (42) at the edge of the conductive strip (17).

公开(公告)号：DE60018121T2

公开(公告)日：2006-01-05

申请号：DE60018121

申请日：2000-02-28

Applicant: LUCENT TECHNOLOGIES INC

Inventor： FRYE ROBERT CHARLES ,  LOW YEE LENG ,  TAI KING LIEN

IPC: H01P11/00 ,  H01P3/08 ,  H05K3/24

Abstract: The specification describes a method for improving the edge acuity of conductive metal strips formed by thick film paste techniques. The advantages of the bulk properties of strips formed using thick film technology are realized while the drawback of poor edge definition is overcome using a thin film trim strip (42) at the edge of the conductive strip (17).