公开(公告)号：JP2002043449A

公开(公告)日：2002-02-08

申请号：JP2001151776

申请日：2001-05-22

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON ,  DUDDERAR THOMAS D ,  TAI KING L

IPC: B81C3/00 ,  B81B7/00 ,  H01L23/02 ,  H01L23/06 ,  H01L31/02

Abstract: PROBLEM TO BE SOLVED: To provide a packaging technology for a MEMS assembly where a MEMS device array is mounted on a silicon wafer platform. SOLUTION: A silicon chamber may is sealed airtightly. By using a package made of only silicon for the MEMS device array, the thermodynamic instability disappears substantially. The mechanical instability is also reduced by using a contact pin array in order to interconnect a silicon supporting substrate for the MEMS device to the next interconnection level. The MEMS device can be detached easily by using the contact pin array for the purpose of replacement or repairing.

公开(公告)号：JP2000091462A

公开(公告)日：2000-03-31

申请号：JP25301799

申请日：1999-09-07

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON ,  DUDDERAR THOMAS D ,  FRYE ROBERT CHARLES ,  TAI KING L

IPC: H01L23/12 ,  H01L23/13 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To mutually wire one IC chip with a translator and obtain high mutual wiring density by a power source and an installation mutual wiring structure, using a power source step and a grounding step made in an isolated multistep structure mutual wiring translator. SOLUTION: A power source and a grounding step are provided with several- step isolated mutual wiring steps 31 to 34 on a translator 21 which is silicon. By a multistep structure mutual wiring feature included in the translator 21, several power source and grounding mutual wiring are adjusted and integrated by this board step. Then, a power source input/output or a grounding input/ output is further coupled to a next board step. Moreover, since the translator 21 accommodates a single multipin IC chip, it is made larger than the IC chip. This large translator region enables leading a pattern and developing it in all direction on the translator 21 made of silicon.

公开(公告)号：JP2002043461A

公开(公告)日：2002-02-08

申请号：JP2000199728

申请日：2000-06-30

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON ,  DUDDERAR THOMAS D ,  FRYE ROBERT CHARLES

IPC: H05K3/34 ,  H01L23/12 ,  H01L23/32

Abstract: PROBLEM TO BE SOLVED: To provide an IC package having a high-density I/O wherein an IC chip is bonded to a silicon intermediate interconnect substrate (IIS) and the IIS is wire-bonded to a printed wiring board(PWB). SOLUTION: This package comprises the PWB having wire-bonding pads on its upper surface, the semiconductor IIS, a means for die-bonding the lower surface of the IIS to the upper surface of the PWB, and a means for wire- bonding the wire-bonding pads on the IIS to the wire-bonding pad on the PWB. Further, the IIS comprises a semiconductor substrate having a center region on its upper surface, IIS interconnect sites on the center region of the upper surface of the semiconductor substrate, the IIS wire-bonding pads around the center region of the upper surface of the semiconductor substrate, and a metallized runner which interconnects the IIS interconnect sites with the IIS wire- bonding pads.

公开(公告)号：JP2001135775A

公开(公告)日：2001-05-18

申请号：JP2000284630

申请日：2000-09-20

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DUDDERAR THOMAS D ,  KOSSIVES DEAN PAUL ,  LOW YEE LENG

IPC: H05K9/00 ,  H01L23/00 ,  H01L23/02 ,  H01L23/055 ,  H01L23/12 ,  H01L23/498 ,  H01L23/552 ,  H01L25/04 ,  H01L25/18 ,  H05K1/02 ,  H05K1/14 ,  H05K3/34

Abstract: PROBLEM TO BE SOLVED: To provide a recessed chip MCM package integrally equipped with an electromagnetic shield. SOLUTION: A surface of a cavity for housing an IC device is coated with a metal. The exposed upper surface and side surface of a multichip module(MCM) package are also metallized. A PCB(printed circuit board) for connection is provided with a solder wall, which seals a gap between an MCM tile and a PCB for connection. A solder wall is formed by using a standard solder bump technique. The seal between the MCM and PCB is formed during the same reflow operation used to flip-chip bond the MCM tile to the PCB.

公开(公告)号：JP2000040898A

公开(公告)日：2000-02-08

申请号：JP14717699

申请日：1999-05-26

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DUDDERAR THOMAS D ,  GUTENTAG CHARLES

IPC: H05K13/02 ,  H01L21/00 ,  H01L21/50 ,  H01L21/60 ,  H01L21/683

Abstract: PROBLEM TO BE SOLVED: To provide a method for mounting a flip chip speedily suited for a flip flop bonding by taking out an IC chip. SOLUTION: A tape system for transportation for a flip-chip assembly device is configured so that a chip 14 is taken out of the reverse side of a tape 13 for transportation. In this case an evacuation head 21 of a take-out device 16 touches the reverse side of the IC chip 14, a die take-out pin 17 pushes up the IC chip 14 and takes it out with the circuit side (where a solder bump is located) of the chip 14 facing downward.

公开(公告)号：JP2001244406A

公开(公告)日：2001-09-07

申请号：JP2001026208

申请日：2001-02-02

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON ,  DUDDERAR THOMAS D ,  TAI KING L

IPC: H01L23/12 ,  H01L23/36 ,  H01L23/50 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34

Abstract: PROBLEM TO BE SOLVED: To provide a multi-chip IC package with high interconnection density. SOLUTION: The upper surface (or lower surface) of a flexible substrate is joined to a rigid support substrate with an opening for accommodating an IC chip that is joined to the upper surface (or lower surface) of the flexible substrate. In a preferred embodiment, a plurality of IC memories are mounted to one surface of the flexible substrate, and at least one logic chip is mounted to the other surface. An extremely thin flexible substrate is used to optimize the through hole interconnection length between the memory element and the logic element. When the logic chip is to be mounted to a hollow part that is formed by an opening by flip chips, a heat sink plate is used to cover the hollow part and at the same time perform efficient thermal contact to the reverse side of the logic chip.

公开(公告)号：JP2001168275A

公开(公告)日：2001-06-22

申请号：JP2000322417

申请日：2000-10-23

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON ,  DUDDERAR THOMAS D ,  TAI KING L

IPC: H01L25/18 ,  H01L21/301 ,  H01L21/304 ,  H01L21/60 ,  H01L23/04 ,  H01L25/065 ,  H01L25/07

Abstract: PROBLEM TO BE SOLVED: To provide a method for lowering the height of a whole IC package in technology for manufacturing the IC package. SOLUTION: The method includes a step for thinning the IC device of a chip form. It is realized in the final stage of assembly, in which a chip is flip chip-fixed to a substrate, and the backside of the chip is exposed due to thinning. When the method is used, the chip of which final thickness is about 2 to 8 mils can be manufactured and the whole thickness of the package is considerably reduced.

公开(公告)号：JPH1116940A

公开(公告)日：1999-01-22

申请号：JP14477898

申请日：1998-05-26

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DEGANI YINON ,  DUDDERAR THOMAS D ,  TAI KING L

IPC: H01L21/60 ,  H01L21/822 ,  H01L23/488 ,  H01L23/498 ,  H01L23/556 ,  H01L25/04 ,  H01L25/18 ,  H01L27/04 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To protect I/O lead wires from an obstacle due to alpha particles by a method wherein memory chips are respectively provided with a semiconductor charge storage site, the soldered interconnection of the memory chips with a substrate for interconnection use is made within a specified value from the charge storage sites and a solder material has a specified lead content. SOLUTION: A plurality of bonded semiconductor chips 12, 13 and 14 are provided on a substrate 11 for interconnection use. The chips 12 and 13 are memory chips and the chip 14 is a logic chip. The memory chips 12 and 13 are respectively provided with a semiconductor charge storage site and are mounted on the substrate 11 using a soldered connection. The soldered interconnection of the chips 12 and 13 with the substrate 11 is made within the extent of at least 5 mills, that is, 0.127 mm, from the semiconductor charge storage sites. Moreover, the lead content of a solder material is less than 5%. As a solder to be used for bonding the chips 12 and 13 to the substrate 11 in such a way, one hardly contains an alpha particle radioactive material is used.