ELECTRONIC PACKAGE HAVING INTEGRATED FILTER

    公开(公告)号:JP2001185654A

    公开(公告)日:2001-07-06

    申请号:JP2000335300

    申请日:2000-11-02

    Inventor: LOW YEE LENG

    Abstract: PROBLEM TO BE SOLVED: To obtain an electronic package assembly having an integrated filter more effectively using a space by obtaining a filter for removing an unnecessary frequency effect in the assembly and necessarily suppressing an increase in its cost in a mass production of the assembly. SOLUTION: The electronic package 100 comprises a substrate 105 for supporting at least one electronic device 110. In this case, the substrate 105 has a transmission line base integrated filter having at least one conductive layers 165, 175, 170 and 180 coupled to the device 110 and integrally formed in or on the substrate. Thus, a band-pass filter is created according to the volume of a conductive trace, the shape of a conductive element 115 and further the shape and the dielectric constant of the package substrate 105.

    INTEGRATED CIRCUIT PACKAGE
    3.
    发明专利

    公开(公告)号:JP2003110087A

    公开(公告)日:2003-04-11

    申请号:JP2002231207

    申请日:2002-08-08

    Abstract: PROBLEM TO BE SOLVED: To provide a multilevel mutual connection assembly of low cost whose structure is simple. SOLUTION: At least a part of an interchip mutual connection circuit is shifted to a smaller (upper part) chip. When a plurality of upper part chips exist, an interchip circuit is designed as if mutual connection circuits on two chips contain a common mutual connection level, i.e., in such a manner that mutual connection to one chip out of upper chips contains a runner on another upper chip. The feature of constitution of this invention is that a gap which has been existed in chip-on-chip bonding is used for providing air insulation type crossover connection.

    INTEGRATED CIRCUIT PACKAGE
    4.
    发明专利

    公开(公告)号:JPH11195746A

    公开(公告)日:1999-07-21

    申请号:JP28571498

    申请日:1998-10-07

    Abstract: PROBLEM TO BE SOLVED: To assemble an inexpensive multi-level mutual connection with a simple structure by shifting at lest a part of an inter-chip mutual connecting circuit to a more smaller upper chip and including a runner on the other upper chip in the mutual connection to one of the upper chips. SOLUTION: A metal layer at a certain level is formed on a support chip. An upper chip 41 has a contact-point pad 62. A mutual connecting circuit at the single level is indicated by runners 63-65. An upper chip 67 undergoes flip- chip connection to a support-chip substrate 61 with solder bumps 68 and 69. An under-bump metablized layer 71 is ranged between the solder bump and the chip surface. In the metallic mutually connecting structure at the single level, runners 72-74 are formed on the upper chip 67. The runner 73 on the surface of the upper chip crosses the runner 64 on the surface of the support chip supported by the solder bumps 68 and 69. This cross-over is insulated with air by a gap 75.

    6.
    发明专利
    未知

    公开(公告)号:DE60018121D1

    公开(公告)日:2005-03-24

    申请号:DE60018121

    申请日:2000-02-28

    Abstract: The specification describes a method for improving the edge acuity of conductive metal strips formed by thick film paste techniques. The advantages of the bulk properties of strips formed using thick film technology are realized while the drawback of poor edge definition is overcome using a thin film trim strip (42) at the edge of the conductive strip (17).

    8.
    发明专利
    未知

    公开(公告)号:DE60018121T2

    公开(公告)日:2006-01-05

    申请号:DE60018121

    申请日:2000-02-28

    Abstract: The specification describes a method for improving the edge acuity of conductive metal strips formed by thick film paste techniques. The advantages of the bulk properties of strips formed using thick film technology are realized while the drawback of poor edge definition is overcome using a thin film trim strip (42) at the edge of the conductive strip (17).

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