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    TITANIUM-TANTALUM BARRIER THIN FILM AND FORMATION METHOD THEREFOR
    1.
    发明专利
    TITANIUM-TANTALUM BARRIER THIN FILM AND FORMATION METHOD THEREFOR 失效

    公开(公告)号：JP2001110751A

    公开(公告)日：2001-04-20

    申请号：JP2000152242

    申请日：2000-05-24

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： BHOWMIK SIDDHARTHA ,  MERCHANT SAILESH M ,  MINSEOKU OO ,  PRADIP KUMAR ROY ,  SEN SIDHARTHA

    IPC: C23C14/14 ,  C23C16/06 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52

    Abstract: PROBLEM TO BE SOLVED: To provide a titanium-tantalum barrier thin film and a method for forming a thin film. SOLUTION: In a titanium-tantalum barrier thin film used together with an interconnecting thin film of copper, a relatively excessive titanium/insufficient tantalum portion is formed near the boundary between the thin film and a dielectric thin film, and a relatively excessive tantalum/insufficient titanium portion is formed near the boundary between the thin film and a conductive interconnecting thin film formed on the barrier layer. Excessive titanium/ insufficient tantalum portion causes the thin film, to firmly stick to the dielectric thin film and the excessive tantalum/insufficient titanium portion suppresses formation of an intermetallic compound by forming a hetero-epitaxial interface with the interconnecting thin film. The single titanium-tantalum thin film, having a compositional gradient from the top to the bottom, can be formed by various techniques including PVD, CVD, sputter deposition using a sputtering target having a uniform composition, and sputter deposition using a plurality of sputtering targets. A synthetic titanium-tantalum thin film is composed of two separately formed thin films.

    METHOD FOR FORMATION OF GATE OXIDE LAYER WITH VARITIES OF THICKNESSES IN GATE-DIELECTRIC STACK STRUCTURE
    3.
    发明专利
    METHOD FOR FORMATION OF GATE OXIDE LAYER WITH VARITIES OF THICKNESSES IN GATE-DIELECTRIC STACK STRUCTURE 失效

    公开(公告)号：JP2001024064A

    公开(公告)日：2001-01-26

    申请号：JP2000123012

    申请日：2000-04-24

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： KIZILYALLI ISIK C ,  MA YI ,  RADOSEVICH JOSEPH R ,  PRADIP KUMAR ROY

    IPC: H01L21/3213 ,  H01L21/316 ,  H01L21/8234 ,  H01L27/088

    Abstract: PROBLEM TO BE SOLVED: To form a gate oxide layer with two types of thicknesses in a semiconductor device by allowing an oxygen diffusion barrier layer to check change of a second thickness of a gate oxide layer during formation of a first thickness of gate oxide. SOLUTION: A gate oxide layer 30 is formed to a predetermined first thickness 32 on a substrate 20, and an oxygen diffusion barrier layer 40 is deposited on the gate oxide layer 30. Thereafter, a photoresist mask is selectively patterned on the barrier layer 40. Then, a photoresist mask is removed, a gate- dielectric stack structure 10 is subjected to thermal oxidation process, and a new gate oxide layer 30 is formed on a first device 50. The gate oxide layer 30 is selectively formed to a second thickness 34 which is different from the first thickness 32. The oxygen diffusion barrier layer 40 deposited on the gate oxide layer 30 of a second device 60 checks further oxidation of the gate oxide layer 30.

    PREPARATION OF MOS DEVICE
    4.
    发明专利
    PREPARATION OF MOS DEVICE 失效

    公开(公告)号：JP2000091579A

    公开(公告)日：2000-03-31

    申请号：JP26060099

    申请日：1999-09-14

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： AISHIKKU C KIZURUYARI ,  MERCHANT SAILESH M ,  PRADIP KUMAR ROY

    IPC: H01L29/78 ,  C23C14/06 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/49

    Abstract: PROBLEM TO BE SOLVED: To prevent boron from diffusing up from the source and drain by making nitride exist in a synthetic gate electrode. SOLUTION: A synthetic gate electrode 16 consists of a tungsten silicide layer 17, formed on the gate dielectric 13 and the tungsten silicide nitride, WSixNy, a layer 18 formed thereon, and all the layers are deposited in one operation process in formation of a synthetic gate electrode layer. Then, an intermediate layer dielectric is deposited after the source 21 and drain 22 are formed through ion implantation, a second layer metal is deposited and subjected to pattern formation, another intermediate layer dielectric is deposited, a source/ drain contact window is shaped. Source and drain contact metallization is deposited and is subjected to pattern formation and contacts 24, 25 for a source and a drain are formed. A tungsten silicide layer is satisfactory in sticking property to a gate dielectric, and a tungsten silicon nitride layer becomes an effective barrier with respect to boron diffusion.

    INTEGRATED CIRCUIT DEVICE WITH COMPOSITE OXIDE DIELECTRIC
    6.
    发明专利
    INTEGRATED CIRCUIT DEVICE WITH COMPOSITE OXIDE DIELECTRIC 未知

    公开(公告)号：SG87073A1

    公开(公告)日：2002-03-19

    申请号：SG200000093

    申请日：2000-01-10

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： SAILESH MANSINH MERCHANT ,  PRADIP KUMAR ROY

    IPC: H01L29/78 ,  H01L21/28 ,  H01L21/77 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L29/94

    Abstract: An integrated circuit device includes a semiconductor substrate (10) and a first metal oxide layer (15) adjacent the substrate. The first metal oxide layer may be formed of tantalum oxide, for example. A second metal oxide layer (17), which includes an oxide with a relatively high dielectric constant such as titanium oxide, zirconium oxide, or ruthenium oxide, is formed on the first metal oxide layer opposite the semiconductor substrate, and a metal nitride layer (19), such as titanium nitride, is formed on the metal oxide layer opposite the first metal oxide layer. The metal nitride layer includes a metal which is capable of reducing the first metal oxide layer. Thus, the second metal oxide layer substantially blocks reduction of the first metal oxide layer by the metal of the metal nitride layer.

    INTEGRATED CIRCUIT CAPACITOR INCLUDING ANCHORED PLUGS
    7.
    发明专利
    INTEGRATED CIRCUIT CAPACITOR INCLUDING ANCHORED PLUGS 未知

    公开(公告)号：SG83177A1

    公开(公告)日：2001-09-18

    申请号：SG200000078

    申请日：2000-01-06

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： SUNDAR SRINIVASAN CHETLUR ,  JAMES THEODORE CLEMENS ,  SAILESH MANSINH MERCHANT ,  PRADIP KUMAR ROY ,  HEM M VAIDYA

    IPC: H01L27/10 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/92

    Abstract: An integrated circuit capacitor includes a substrate (24), a first dielectric layer (26) adjacent the substrate and having a first trench (28) therein, and a first metal plug (30) extending upwardly from the substrate into the first trench. An interconnection line (32) overlies the first trench and contacts the first metal plug to define anchoring recesses (34) on opposite lateral sides of the first metal plug. A second dielectric layer (36) is on the interconnection line and has a second trench (38) therein. A second metal plug (22) extends upwardly into the second trench. More particularly, the second metal plug includes a body portion (40) extending upwardly into the second trench, and anchor portions (42) connected to the body portion and engaging the anchoring recesses to anchor the second metal plug to the interconnection line. The capacitor stack (44,48,46) overlies the second trench and contacts the second metal plug. Because the second metal plug is anchored, a depth of the second trench can be greater, thereby increasing the surface area of the capacitor, without the metal plug becoming loose and separating from the underlying interconnection line.

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