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    MANUFACTURE OF SCHOTTKY GATE TRANSISTOR
    1.
    发明专利
    MANUFACTURE OF SCHOTTKY GATE TRANSISTOR 失效

    公开(公告)号：JPH11150130A

    公开(公告)日：1999-06-02

    申请号：JP26705298

    申请日：1998-09-21

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： LOTHIAN JAMES ROBERT ,  REN FAN

    IPC: H01L21/027 ,  H01L21/285 ,  H01L21/335 ,  H01L21/338 ,  H01L29/423 ,  H01L29/778 ,  H01L29/812

    Abstract: PROBLEM TO BE SOLVED: To obtain a semiconductor element having a T-shaped feature in the vertical direction by specifying the T-shaped feature through the use of a thick photoresist layer having two levels, forming a contact structure by depositing a metal for gate contact in the T-shaped feature, and then hardening the photoresist after patterning the photoresist by photolithography. SOLUTION: In a T-shaped Schottky gate structure used for group III-V field effect transistor device, a gate is formed on an active layer 12 in a recessed state by wet-etching a window in a cap layer 13. When the Schottky gate 17 for MESFET device is reverse biased, an n-type carrier is depleted from a depletion region 18 below the Schottky gate, and such a p-type region that pinches off the flow between a source and drain is formed. The T-shape of the gate is prescribed to be vertical and to have a vertical section 21 and a horizontal section 22.

    METHOD FOR MANUFACTURING SEMICONDUCTOR LASER OF GAAS BASE
    2.
    发明专利
    METHOD FOR MANUFACTURING SEMICONDUCTOR LASER OF GAAS BASE 失效

    公开(公告)号：JPH1075020A

    公开(公告)日：1998-03-17

    申请号：JP20666997

    申请日：1997-07-31

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： CHAKRABARTI UTPAL KUMAR ,  HOBSON WILLIAM SCOTT ,  REN FAN ,  SCHNOES MELINDA LAMONT

    IPC: H01L33/00 ,  H01S5/00 ,  H01S5/02 ,  H01S5/028 ,  H01S5/223 ,  H01S5/343 ,  H01S3/18

    Abstract: PROBLEM TO BE SOLVED: To provide a process where a passivation layer is formed at a facet by, when an inductive layer is deposited, allowing a cleavage plane to be exposed to specific plasma in a deposition chamber, so that the inductive layer is deposited on the cleavage face, without exposing a laser bar to the atmosphere. SOLUTION: After completion of manufacturing a multi-layer ware which was mesa-etched and metalized, a line is engraved in the surface of wave, so that individual semiconductor chip is regulated (110), to be cleaved along surface, thus defining a laser bar. Then after a jig with the laser bar mounted is assigned in a reactive chamber, the inside of the chamber is evacuated to 10 Torr or below, and the laser bar exposed to passivation plasma of H2 S. Hydrogen in the plasma removes inherent oxide from a facet surface, and sulfur in the plasma combines to Ga and As, thus a surface state density of the facet decreases. After exposed to H2 S plasma, a protective inductive layer is deposited on the facet.

    ARTICLE WITH SEMICONDUCTOR DEVICE
    4.
    发明专利
    ARTICLE WITH SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JPH11243088A

    公开(公告)日：1999-09-07

    申请号：JP28705698

    申请日：1998-10-08

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： HOBSON WILLIAM SCOTT ,  HONG MINGHWEI ,  LOTHIAN JAMES ROBERT ,  MANNAERTS JOSEPH P ,  REN FAN

    IPC: H01L29/78 ,  H01L21/20 ,  H01L21/28 ,  H01L21/316 ,  H01L29/51 ,  H01L29/786

    Abstract: PROBLEM TO BE SOLVED: To allow high-quality oxide to grow on GaN by providing a GaGd oxide layer on the surface of a GaN semiconductor body for a semiconductor device. SOLUTION: A GaN body 12 is prepared, and finished into a surface where the related part of the surface of the body 12 is in a primitive level, is clean, and at the same time is in order with the primitive level. Then, before approximately 1% of a dust surface is covered with an impurity atom, the first monolayer of oxide is formed, an oxide layer 13 is formed by a process where the related part of the surface being in a primitive level, clean, and at the same time, in order with the primitive level is subjected to deposit from the deposition source of Ga5 Gd3 O12 so that a GaGd oxide layer grows up to a specific thickness. Also, the GaN body is a single crystal body, and the main surface has (0001) orientation or an orientation close to the (0001) orientation (namely, within 5 deg.C).

    INTEGRATED CIRCUIT DEVICE
    5.
    发明专利
    INTEGRATED CIRCUIT DEVICE 失效

    公开(公告)号：JPH11204646A

    公开(公告)日：1999-07-30

    申请号：JP28452298

    申请日：1998-10-06

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： KOSSIVES DEAN PAUL ,  REN FAN ,  TAI KING L

    IPC: H05K1/11 ,  H01L21/60 ,  H01L21/768 ,  H01L23/14 ,  H01L23/485 ,  H01L23/522 ,  H01L23/538 ,  H01L25/00

    Abstract: PROBLEM TO BE SOLVED: To improve air insulation crossover through multi-chip module technology by bonding a flip-chip on a substrate for interconnection, and forming an air bridge between the flip-chip and the substrate for interconnection in a transistor IC. SOLUTION: A silicon-made substrate 51 for interconnection is provided with an oxide layer 52, which covers the substrate 51 for interconnection and a semiconductor chip 11 of an IC chip is mounted on the substrate 52 by a flip-chip assembly 62 via the oxide layer 52. Then, an air insulation type crossover region is formed as an air bridge for the semiconductor chip 11 via plating balls 56 and a layer 55. At this time, the flip-chip assembly 62 which is a module for interconnection constitutes a silicon chip having an oxide layer 63, the layer 55, and an underbump metal layer 64. As a result of this method, air insulation crossover can be improved with the use of multi-chip module technology.

    MOSFET ON THE BASIS OF GALLIUM ARSENIC AND ITS PRODUCT
    6.
    发明专利
    MOSFET ON THE BASIS OF GALLIUM ARSENIC AND ITS PRODUCT 失效

    公开(公告)号：JPH10242465A

    公开(公告)日：1998-09-11

    申请号：JP4168598

    申请日：1998-02-24

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： CHO ALFRED Y ,  HONG MINGHWEI ,  JAMES ROBERT ROSHIAN ,  MANNAERTS JOSEPH P ,  REN FAN

    IPC: H01L29/78 ,  B82B1/00 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/51

    Abstract: PROBLEM TO BE SOLVED: To form the alloy of an ohmic metal contact by allowing a gate oxide layer of a product including a metal/oxide/semiconductor field effect transistor on the basis of a first GaAs where a gate metal contact is arranged on a gate oxide layer as a base to be Gd-Ga oxide with a specific Gd:Ga atom ratio. SOLUTION: A protection dielectric layer is formed by depositing SiO2 . The formation of an alloy of an ohmic metal is performed at a temperature within a range of, for example, 400±50 deg.C in He atmosphere in a typical case. The elimination of the protection dielectric requires strictness for preventing the gate oxide from being damaged. More specifically, the composition of the gate oxide is selected properly, namely a Gd-Ga oxide with a Gd-Ga ratio that is 1:7.5 or preferably 1:4 or 1:2 or larger. The etching speed of Gd-Ga oxide in an HF solution depends on the Gd content of the oxide. Therefore, the protection dielectric on the gate oxide can be eliminated without losing the gate oxide and the alloy of the ohmic metal contact can be formed.

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