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公开(公告)号:CA873593A
公开(公告)日:1971-06-15
申请号:CA873593D
Applicant: MATSUSHITA ELECTRONICS CORP
Inventor: FUJIWARA SHOHEI , HASEGAWA HIROMASA , IIZUKA MUTSUO , TERAMOTO IWAO , IWASA HITOO , KANO GOTA
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公开(公告)号:CA858744A
公开(公告)日:1970-12-15
申请号:CA858744D
Applicant: MATSUSHITA ELECTRONICS CORP
Inventor: KANO GOTA , IIZUKA MUTSUO , SAWAKI TSUKASA , FUJIWARA SHOHEI , HASEGAWA HIROMASA
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公开(公告)号:CA859942A
公开(公告)日:1970-12-29
申请号:CA859942D
Applicant: MATSUSHITA ELECTRONICS CORP
Inventor: KANO GOTA , IIZUKA MUTSUO , FUJIWARA SHOHEI , SAWAKI TSUKASA , HASEGAWA HIROMASA
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公开(公告)号:CA875237A
公开(公告)日:1971-07-06
申请号:CA875237D
Applicant: MATSUSHITA ELECTRONICS CORP
Inventor: KANO GOTA , FUJIWARA SHOHEI , SAWAKI TSUKASA , HASEGAWA HIROMASA , IIZUKA MUTSUO
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公开(公告)号:DE1949646A1
公开(公告)日:1970-04-30
申请号:DE1949646
申请日:1969-10-01
Applicant: MATSUSHITA ELECTRONICS CORP
Inventor: IIZUKA MUTSUO , FUJIWARA SHOHEI , HASEGAWA HIROMASA , IWASA HITOO , KANO GOTA , TERAMOTO IWAO
IPC: C23F1/02 , C23F1/40 , H01L21/00 , H01L21/306 , H01L23/485 , H01L29/47 , H01L29/872 , H01L7/34
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公开(公告)号:DE1941911A1
公开(公告)日:1970-03-05
申请号:DE1941911
申请日:1969-08-18
Applicant: MATSUSHITA ELECTRONICS CORP
Inventor: KANO GOTA , IIZUKA MUTSUO , FUJIWARA SHOHEI , HASEGAWA HIROMASA , SAWAKI TSUKASA
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公开(公告)号:CA903378A
公开(公告)日:1972-06-20
申请号:CA903378D
Applicant: MATSUSHITA ELECTRONICS CORP
Inventor: YOKOZAWA MASAMI , KANO GOTA , FUJIWARA SHOHEI , IIZUKA MUTSUO , TAKAMURA TORU
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公开(公告)号:GB1277686A
公开(公告)日:1972-06-14
申请号:GB2260070
申请日:1970-05-11
Applicant: MATSUSHITA ELECTRONICS CORP
Inventor: YOKOZAWA MASAMI , KANO GOTA , FUJIWARA SHOHEI , TAKAMURA TORU , IIZUKA MUTSUO
Abstract: 1277686 Semi-conductor devices MATSUSHITA ELECTRONICS CORP 11 May 1970 [13 May 1969] 22600/70 Heading H1K A PNP transistor (Fig. 6) comprises an N- layer 2 formed epitaxially or by diffusion on a P-silicon substrate 1, an insulating oxide layer 3 formed by pyrolysis of organo oxysilane on the N-layer, an annular window 4 opened in the oxide film and etched to a ditch in the N-layer, a diffusion window 5 opened within the ditch and boron diffused into the window and the ditch simultaneously to form an emitter region 6 and a separation layer 7; the ditch depth being less than the thickness of the N-layer so that the sum of ditch depth and layer thickness exceeds that of the N-layer; the base collector junction being separated from the exposed edge. A pressure-sensitive transistor (Fig. 7, not shown) comprises electrodes applied to the substrate and the emitter region and a Schottky junction base electrode of e.g. molybdenum film applied to the base region of the epitaxial layer, to which pressure means is applied to vary the charge injected into the base and thus the output voltage/current characteristic. A P-type separation layer is formed simultaneously with the emitter diffusion in a planar PNP-transistor to divide the base-collector junction.
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公开(公告)号:DE2023153A1
公开(公告)日:1970-11-26
申请号:DE2023153
申请日:1970-05-12
Applicant: MATSUSHITA ELECTRONICS CORP
Inventor: YOKOZAWA MASAMI , IIZUKA MUTSUO , KANO GOTA , FUJIWARA SHOHEI , TAKAMURA TORU
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公开(公告)号:DE1949647A1
公开(公告)日:1970-04-09
申请号:DE1949647
申请日:1969-10-01
Applicant: MATSUSHITA ELECTRONICS CORP
Inventor: KANO GOTA , FUJIWARA SHOHEI , HASEGAWA HIROMASA , IIZUKA MUTSUO , SAWAKI TSUKASA
IPC: A01D41/127 , H01L23/485 , H01L29/00 , H04R23/00 , H01L5/06
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