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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US3922710A

    公开(公告)日：1975-11-25

    申请号：US46631974

    申请日：1974-05-02

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： KOIKE SUSUMU

    IPC: G11C16/04 ,  H01L23/29 ,  H01L29/00 ,  H01L29/792 ,  H03K3/26 ,  H03K3/356 ,  H01L29/88 ,  H01L29/34 ,  H01L29/78 ,  H01L29/90

    CPC classification number: H03K3/356008 ,  G11C16/0466 ,  H01L23/291 ,  H01L24/06 ,  H01L29/00 ,  H01L29/792 ,  H01L2924/12036 ,  H01L2924/1306 ,  H03K3/26 ,  H03K3/356 ,  Y10S148/114 ,  H01L2924/00

    Abstract: A first thin insulating film capable of being pierced or punched through by carriers such as an SiO2 film 20 A thick is deposited on the surface of a P-type silicon substrate and a second insulating film with a trap level such as an Si3N4 film 500 to 600 A thick is laid on the first insulating film. Upon application of an electric field through a metal electrode mounted on the second insulating film to the combination of the insulating films, electrons captured at the trap level of the second insulating film transfer through the first insulating film to the surface of the substrate thereby forming an inversion layer. When the inversion layer is connected with the two junction regions formed in the surface of the substrate, the reverse current level of the junction region increases semipermanently due to the breakdown voltage of the junction until the inversion layer is cancelled by the application of a reverse electric field. This principle is used to produce a memory device characterized by an exact operation comprising a semiconductor, the first thin insulating film, the second insulating film with a trap level, the second insulating film, the metal electrode and two PN junctions which have different junction breakdown voltages.

    Abstract translation: 能够通过诸如SiO 2膜厚度为20A的载体刺穿或穿孔的第一薄薄绝缘膜沉积在P型硅衬底的表面和具有陷阱水平的第二绝缘膜，例如Si 3 N 4膜500至 第一绝缘膜上放置厚度为600。 当通过安装在第二绝缘膜上的金属电极施加电场到绝缘膜的组合时，在第二绝缘膜的陷阱电平处捕获的电子通过第一绝缘膜转移到基板的表面，从而形成 逆温层。 当反型层与形成在衬底的表面中的两个结区连接时，结区的反向电流水平由于结的击穿电压而长时间增加，直到通过施加反向电 领域。 该原理用于制造存储器件，其特征在于精确的操作，其包括半导体，第一薄绝缘膜，具有陷阱级的第二绝缘膜，第二绝缘膜，金属电极和具有不同结断层的两个PN结 电压。

    NEGATIVE RESISTANCE DEVICE USING COMPLEMENTARY FET'S
    2.
    发明专利
    NEGATIVE RESISTANCE DEVICE USING COMPLEMENTARY FET'S 未知

    公开(公告)号：CA1077622A

    公开(公告)日：1980-05-13

    申请号：CA246101

    申请日：1976-02-19

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： KOIKE SUSUMU ,  KANO GOTA ,  TERAMOTO IWAO

    IPC: G11C11/36 ,  G11C14/00 ,  H01L27/06 ,  H01L27/092 ,  H03K3/3565 ,  G11C11/40 ,  H03K3/353

    Abstract: A negative resistance device is formed by a series-connection of a complementary pair of insulated gate type FETs (field effect transistors), the sources of the FETs being connected to each other and the gate of each FET being connected to the drain of the other FET. At least one of the FETs has a double layered gate insulating film under the gate electrode, thereby forming a non-volatile memory element. The device acquires or loses a negative resistance characteristic by responding to signals on the gates, thereby memorizing the signals. A highly efficient memory which requires little power during writing-in, erasing and memory-holding, can be achieved in this way.

    4.
    发明专利
    未知

    公开(公告)号：DE2606744A1

    公开(公告)日：1976-09-02

    申请号：DE2606744

    申请日：1976-02-19

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： KOIKE SUSUMU ,  KANO GOTA ,  TERAMOTO IWAO

    IPC: G11C11/36 ,  G11C14/00 ,  H01L27/06 ,  H01L27/092 ,  H03K3/3565 ,  G11C11/40 ,  H01L27/08

    Abstract: 1520067 Semiconductor devices MATSUSHITA ELECTRONICS CORP 19 Feb 1976 [20 Feb 1975 18 April 1975 17 Sept 1975] 06656/76 Heading H1K [Also in Division H3] A negative resistance device comprises a complementary pair of depletion mode FETs 20, 30 whose sources 25, 35 are connected together and the drain 26, 36 of each FET is connected to the gate 24, 34 of the other FET, at least one of the FETs 20, 30 having a gate insulation which stores electric charges so as to memorize in a non-volatile manner. The FETs 20, 30 may be MNOS devices with polysilicon gates and a Si substrate, or alternatively, the gate insulation may be a Al 2 O 3 -SiO 2 double layer. In other embodiments the substrate 21 is connected to the sources 25, 35 and a diode in series with either drain is formed by doping the drain. This reduces the current required to read the state of the FET to zero. In another embodiment a well 31 in which one FET 30 is formed also serves as the source of the other FET 20.

    PLANAR STRUCTURE SEMICONDUCTOR DEVICE
    6.
    发明专利
    PLANAR STRUCTURE SEMICONDUCTOR DEVICE 未知

    公开(公告)号：CA967275A

    公开(公告)日：1975-05-06

    申请号：CA135293

    申请日：1972-02-22

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： FUJIWARA SHOHEI ,  KOIKE SUSUMU

    IPC: H01L21/00 ,  H01L21/316 ,  H01L29/00 ,  H01L33/30 ,  H01L47/00

    Abstract: 1359579 Semi-conductor devices MATSUSHITA ELECTRONICS CORP 18 Feb 1972 [23 Feb 1971 (2)] 7667/72 Heading H1K A region 5 of a III-V semi-conductor body 1 is formed by diffusion of a dopant such as Zn or Cd through a layer 2 of Ta, Nb, Ti, Zr or Hf surrounded by a layer 4 of an oxide of the metal of layer 2, the oxide being impermeable to the diffusing dopant. The oxide 4 is preferably formed by selective anodization of the metal layer 2. In the GaAs light-emitting diode shown the original body 1 is Te-doped and N- type, the Ta layer 2 being applied by sputtering. An ohmic Au-Cr alloy electrode 7 on the layers 2 and 4 is soft-soldered to a Cu heat sink 9, and an annular Au-Ge ohmic electrode is formed on the substrate 1, both electrodes being formed by evaporation. In a modification the P + diffused region may be formed in a P-type liquid-phaseepitaxially grown layer on an N type substrate. GaP, GaAs 1-x P x , Ga 1-x Al x As and Ga 1-x Al x P are other suitable semi-conductors, and the invention is also applicable to the manufacture of IMPATT diodes.

    8.
    发明专利
    未知

    公开(公告)号：DE2657415A1

    公开(公告)日：1977-07-07

    申请号：DE2657415

    申请日：1976-12-17

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： KANBARA GINJIRO ,  KOIKE SUSUMU ,  MATSUDA TOSHIO

    IPC: H01L21/225

    Abstract: A silicon oxide layer containing a group III element such as boron, aluminum or gallium is formed on a semiconductor substrate. The substrate is then heat treated at 600 DEG C - 1200 DEG C in a nitrogen atmosphere and a diffusion process carried out thereafter. In this manner, the impurity diffused surface of the semiconductor body is controlled to a low concentration not higher than 1018/cm3 of the group III element. This is due to the fact that the silicon oxide layer containing the group III element (that is, the so-called doped oxide) is partly converted to a nitride in the course of an ammonia treatment resulting in an impurity source for the low concentration diffusion. The present method is useful in forming the base region of an NPN transistor, for example.

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