公开(公告)号：US3764864A

公开(公告)日：1973-10-09

申请号：US3764864D

申请日：1967-03-21

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： OKUMURA T ,  TSUCHITANI A ,  HASEGAWA T

IPC: H01L27/02 ,  H01L11/00 ,  H01L15/00

CPC classification number: H01L27/0255

Abstract: An insulated gate field-effect transistor constructed by forming, in a portion of the semiconductor substrate close to the source region, a region which constitutes a p-n junction with the substrate, and by connecting this latter region to the gate electrode, whereby there is caused, between said region and the source, a current due to punch-through at high gate voltage so that the breakdown of the transistor is prevented.

Abstract translation: 一种绝缘栅场效应晶体管，其通过在靠近源极区域的半导体衬底的一部分中形成与衬底构成pn结的区域，并将后一区域连接到栅极电极，由此产生 在所述区域和源极之间，由于在高栅极电压下穿通导致的电流，从而防止了晶体管的击穿。

公开(公告)号：SE337262B

公开(公告)日：1971-08-02

申请号：SE397667

申请日：1967-03-21

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： OKUMURA T

IPC: H01L23/485 ,  H01L29/06 ,  H01L29/78 ,  H01L11/14

Abstract: A multi-polar insulated gate transistor having two or more isolated electrodes formed on an insulated film, and an island region having a conductivity type different from that of the semiconductor proper and located in the portion of the substrate beneath said film and below the gap between said electrodes, whereby a large current can flow through the element located closer to the drain when the respective elements which may consist of the pair, i.e., each gate and source-island, island-island or island-drain are under identical voltage conditions.

公开(公告)号：SE307198B

公开(公告)日：1968-12-23

申请号：SE427067

申请日：1967-03-29

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： HASEGAWA T ,  OKUMURA T ,  TSUCHITANI A

IPC: H01L27/02 ,  H01L11/14

Abstract: An insulated gate field-effect transistor constructed by forming, in a portion of the semiconductor substrate close to the source region, a region which constitutes a p-n junction with the substrate, and by connecting this latter region to the gate electrode, whereby there is caused, between said region and the source, a current due to punch-through at high gate voltage so that the breakdown of the transistor is prevented.

公开(公告)号：SE347393B

公开(公告)日：1972-07-31

申请号：SE1286769

申请日：1969-09-18

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： OKUMURA T

IPC: H01L27/088 ,  H03D7/12 ,  H01L19/00 ,  H03D7/14

Abstract: 1280047 FET frequency changer circuits MATSUSHITA ELECTRONICS CORP 16 Sept 1969 [19 Sept 1968] 45493/69 Heading H3T [Also in Division H1] A frequency changer has two IGFETs connected with their sources and drains in parallel and a third IGFET connected in series to the shared drain connection of the other two. The output from a local oscillator is fed to the gate of one of the pair and the input signal is fed to that of the other. Alternatively the one of the pair may itself constitute the local oscillator. As shown a particular embodiment uses triode IGFETs but one or more tetrodes may be used. The particular embodiment is integrated in a single semiconductor wafer which has in one surface a central region 15 of opposite conductivity type to the bulk and constituting the drain of the third IGFET, a spaced surrounding region 12 constituting both the source of T 3 and the shared drains of T 1 and T 2 . A further region 10 surrounds these and constitutes the shared source of T 1 and T 2 . The gate electrode 14 of T 3 is a closed figure and the U-shaped gate electrodes 11, (13) of T 1 and T 2 together have a similar shape to electrode 14. In N-channel depletion mode devices especially, highly doped anti-inversion regions 16, 17 are formed in the substrate to complete the closed figure otherwise formed by the gates 11, 13 of T 1 and T 2 .

公开(公告)号：SE313879B

公开(公告)日：1969-08-25

申请号：SE427167

申请日：1967-03-29

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： OKUMURA T

IPC: H01L23/485 ,  H01L29/06 ,  H01L29/78 ,  H01L11/14

Abstract: 1,132,810. Field effect transistors. MATSUSHITA ELECTRONICS CORP. 14 March, 1967 [30 March, 1966], No. 11894/67. Heading H1K. A field effect transistor comprises at least two insulated gates with one or two " island " regions of conductivity type opposite to that of the main channel intermediate the source and drain and underlying part of each gate electrode and an insulated shield electrode overlying the centre of the islands. Fig. 1 shows a section through a field effect transistor comprising source region 1, drain region 3 and " island " region 2 all of a conductivity type opposite to that of the substrate 7. A first gate electrode 4 and a second gate electrode 6 on oxide layer 8 overlie the channel regions between source and island and island and drain respectively. A shield electrode 5 on the oxide layer overlies the " island " region 2; when this shield electrode is grounded or connected to source 1, the capacity between the first and second gates is reduced and separate input signals may be applied to these gates. The thickness of the oxide layer may be made thinner under the shield electrode or under one of the gate electrodes to vary the capacitative and control effect. The arrangement effectively provides two field effect transistors 1, 4, 2 and 2, 6, 3 and the lengths of the two channels (sourceisland and island-drain) may be made different to provide different saturation current characteristics. A further " island " and a third gate may also be provided and embodiments comprising annular or U-shaped zones and electrodes are also described. The semiconductor material may consist of silicon, germanium, cadmium sulphide, or gallium arsenide and the insulating layer of SiO, SiO 2 , silicon nitride or magnesium fluoride.

公开(公告)号：SE324186B

公开(公告)日：1970-05-25

申请号：SE397467

申请日：1967-03-21

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： ARITA S ,  KAMEI I ,  OKUMURA T

IPC: H01L21/306 ,  C23F1/02 ,  H01L21/00 ,  H01L21/033 ,  H01L21/316 ,  H01L23/29 ,  H01L7/50