公开(公告)号：JPH11224192A

公开(公告)日：1999-08-17

申请号：JP30756098

申请日：1998-10-28

Applicant: MICROCHIP TECH INC

Inventor： DRAKE RODNEY J ,  YACH RANDY L ,  TRIECE JOSEPH W ,  CHIAO JENNIFER ,  WOJEWODA IGOR ,  ALLEN STEVE

IPC: G06F9/32 ,  G06F9/34 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To increase a memory base capable of addressing by providing a second address bus for supplying all the address values of a two-word instruction to a linearized program memory in one cycle. SOLUTION: A first address bus 14 is connected to the linearized program memory 12 and is used for sending the address of a fetched instruction to the linearized program memory 12. A pointer 16 is connected to the first address bus 14. The second address bus 20 is provided with a first end part connected to the output of the linearized program memory 12 and the second end part of the second address bus 20 is connected to the first address bus 14. The second address bus 20 is used for arranging the address of the operand of the second word (word fetched during the execution of a first word) of the two-word instruction on the first address bus 14 after the address of the operand of the first word of the two-word instruction is arranged on the first address bus 14.

公开(公告)号：AT204393T

公开(公告)日：2001-09-15

申请号：AT98119390

申请日：1998-10-14

Applicant: MICROCHIP TECH INC

Inventor： DRAKE RODNEY J ,  CHIAO JENNIFER ,  YACH RANDY L ,  WOJEWODA IGOR ,  TRIECE JOSEPH W ,  ALLEN STEVE

IPC: G06F9/32 ,  G06F9/34 ,  G06F9/38

Abstract: A system for allowing a two word instruction to be executed in a single cycle thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word instruction onto the first address bus after an address of an operand of a first word of the two word instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word instruction in a single cycle.

公开(公告)号：ES2165651T3

公开(公告)日：2002-03-16

申请号：ES98119390

申请日：1998-10-14

Applicant: MICROCHIP TECH INC

Inventor： DRAKE RODNEY J ,  CHIAO JENNIFER ,  YACH RANDY L ,  WOJEWODA IGOR ,  TRIECE JOSEPH W ,  ALLEN STEVE

IPC: G06F9/32 ,  G06F9/34 ,  G06F9/38

Abstract: A system for allowing a two word instruction to be executed in a single cycle thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word instruction onto the first address bus after an address of an operand of a first word of the two word instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word instruction in a single cycle.

公开(公告)号：DE69801355D1

公开(公告)日：2001-09-20

申请号：DE69801355

申请日：1998-10-14

Applicant: MICROCHIP TECH INC

Inventor： DRAKE J ,  CHIAO JENNIFER ,  YACH RANDY L ,  WOJEWODA IGOR ,  TRIECE JOSEPH W ,  ALLEN STEVE

IPC: G06F9/32 ,  G06F9/34 ,  G06F9/38

Abstract: A system for allowing a two word instruction to be executed in a single cycle thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word instruction onto the first address bus after an address of an operand of a first word of the two word instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word instruction in a single cycle.

公开(公告)号：DE69801355T2

公开(公告)日：2002-06-13

申请号：DE69801355

申请日：1998-10-14

Applicant: MICROCHIP TECH INC

Inventor： DRAKE J ,  CHIAO JENNIFER ,  YACH RANDY L ,  WOJEWODA IGOR ,  TRIECE JOSEPH W ,  ALLEN STEVE

IPC: G06F9/32 ,  G06F9/34 ,  G06F9/38

Abstract: A system for allowing a two word instruction to be executed in a single cycle thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word instruction onto the first address bus after an address of an operand of a first word of the two word instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word instruction in a single cycle.