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    DATA POINTER TO OUTPUT INDIRECT ADDRESSING MODE ADDRESS WITHIN SINGLE CYCLE AND ITS METHOD
    1.
    发明专利
    DATA POINTER TO OUTPUT INDIRECT ADDRESSING MODE ADDRESS WITHIN SINGLE CYCLE AND ITS METHOD 失效

    公开(公告)号：JPH11232100A

    公开(公告)日：1999-08-27

    申请号：JP30756298

    申请日：1998-10-28

    Applicant: MICROCHIP TECH INC

    Inventor： DRAKE RODNEY J ,  TRIECE JOSEPH W ,  WOJEWODA IGOR ,  JOHANSEN DARREL ,  YACH RANDY L ,  BOLES BRIAN

    IPC: G06F9/35

    Abstract: PROBLEM TO BE SOLVED: To generate an indirect addressing mode address by providing a multiplexer circuit connected to the respective output terminals of a data pointer register, an incrementer and an adder. SOLUTION: A data pointer register 12 stores the current address of an operand used in a simple indirect addressing mode. An incrementer 14 increases the current address of the operand stored in the data pointer register 12. An adder 16 adds the current address and an offset value stored in the data pointer register 12. A multiplexer circuit 18 having a first input terminal connected to the output terminal of the data pointer register 12, a second input terminal connected to the output terminal of the incrementer 14 and a third input terminal connected to the output terminal of the adder 16 selects a desired generated indirect addressing mode address and outputs the selected address to an instruction register.

    SYSTEM FOR ENABLING EXECUTION OF TWO WORD INSTRUCTION IN ONE CYCLE AND METHOD THEREFOR
    2.
    发明专利
    SYSTEM FOR ENABLING EXECUTION OF TWO WORD INSTRUCTION IN ONE CYCLE AND METHOD THEREFOR 失效

    公开(公告)号：JPH11224192A

    公开(公告)日：1999-08-17

    申请号：JP30756098

    申请日：1998-10-28

    Applicant: MICROCHIP TECH INC

    Inventor： DRAKE RODNEY J ,  YACH RANDY L ,  TRIECE JOSEPH W ,  CHIAO JENNIFER ,  WOJEWODA IGOR ,  ALLEN STEVE

    IPC: G06F9/32 ,  G06F9/34 ,  G06F9/38

    Abstract: PROBLEM TO BE SOLVED: To increase a memory base capable of addressing by providing a second address bus for supplying all the address values of a two-word instruction to a linearized program memory in one cycle. SOLUTION: A first address bus 14 is connected to the linearized program memory 12 and is used for sending the address of a fetched instruction to the linearized program memory 12. A pointer 16 is connected to the first address bus 14. The second address bus 20 is provided with a first end part connected to the output of the linearized program memory 12 and the second end part of the second address bus 20 is connected to the first address bus 14. The second address bus 20 is used for arranging the address of the operand of the second word (word fetched during the execution of a first word) of the two-word instruction on the first address bus 14 after the address of the operand of the first word of the two-word instruction is arranged on the first address bus 14.

    PROCESSOR ARCHITECTURE SCHEME HAVING MANY BANK ADDRESS VALUE SUPPLY SOURCES AND METHOD THEREOF
    3.
    发明专利
    PROCESSOR ARCHITECTURE SCHEME HAVING MANY BANK ADDRESS VALUE SUPPLY SOURCES AND METHOD THEREOF 失效

    公开(公告)号：JPH11316679A

    公开(公告)日：1999-11-16

    申请号：JP30756198

    申请日：1998-10-28

    Applicant: MICROCHIP TECH INC

    Inventor： WOJEWODA IGOR ,  DRAKE RODNEY J ,  MITRA SUMIT

    IPC: G06F9/34 ,  G06F9/30 ,  G06F9/35 ,  G06F12/06

    Abstract: PROBLEM TO BE SOLVED: To encode many addressing modes and also to have many bank address value generation sources by preparing a data memory having plural data banks, a selection circuit which selects one of bank address value generation sources, a bank selection register and an instruction register. SOLUTION: A data memory 12 is connected to a CPU to store and transfer data. One of plural banks of the memory 12 serves as a general-purpose/special register. A selection circuit 14 selects one of many bank address value generation sources. A bank selection register 18 supplies a bank address value for an instruction that is executed in a direct short addressing mode. An instruction register 22 supplies a bank address value for an instruction that is executed in a direct long addressing mode and also supplies a bank address value for an instruction that is executed in a direct short addressing mode.

    PREDECODED STACK POINTER ACCOMPANIED BY POST INCREMENT/ DECREMENT ACTION
    4.
    发明专利
    PREDECODED STACK POINTER ACCOMPANIED BY POST INCREMENT/ DECREMENT ACTION 失效

    公开(公告)号：JPH11265287A

    公开(公告)日：1999-09-28

    申请号：JP30756398

    申请日：1998-10-28

    Applicant: MICROCHIP TECH INC

    Inventor： ALLEN STEPHEN ,  WOJEWODA IGOR

    IPC: G06F9/42 ,  G06F7/78 ,  G06F9/32 ,  G06F9/38

    Abstract: PROBLEM TO BE SOLVED: To make predecodable the decrement value of a stack memory by selecting one of the next unused position in a stack memory device or a position immediately before the next unused position in the stack memory. SOLUTION: The stack pointer 12 is used for generating the next unused position in the stack memory device and indicating a place to write a present value in a program counter. The stack pointer 12 further generates the position immediately before the next unused position and reads the final value of the program counter written in the stack memory device. The next unused position in the stack memory device is selected for a write operation and the position immediately before the next unused position in the stack memory device is selected for a read operation. After executing a present instruction, the stack point 12 further performs one of the post increment or post decrement operations at the next unused position in the stack memory.

    5.
    发明专利
    未知

    公开(公告)号：AT506749T

    公开(公告)日：2011-05-15

    申请号：AT07762367

    申请日：2007-05-31

    Applicant: MICROCHIP TECH INC

    Inventor： WOJEWODA IGOR ,  BOLES BRIAN ,  BRADLEY STEVE ,  KAVAIYA GAURANG

    IPC: H03K19/0175

    Abstract: Peripheral functions of an integrated circuit device may be pooled and dynamically mapped to available external input-output connections of the integrated circuit device by using a set of configuration registers. To provide system robustness, the configuration registers may implement various levels of write protection, error correction and monitoring circuitry. One or more peripheral output functions may be mapped to one or more external output connections. Not more than one output function may be active at the same time on the same output connection. Outputs and inputs may be mapped to the same external input-output connection with or without the output being controllable for placement into an inactive state, e.g., high impedance or open collector. When the input is required to receive external data over the external input-output connection, the output may be placed into the inactive state.

    6.
    发明专利
    未知

    公开(公告)号：DE69808020T2

    公开(公告)日：2003-05-22

    申请号：DE69808020

    申请日：1998-10-14

    Applicant: MICROCHIP TECH INC

    Inventor： DRAKE RODNEY J ,  TRIECE JOSEPH W ,  YACH RANDY L ,  BOLES BRIAN ,  WOJEWODA IGOR ,  JOHANSEN DARREL

    IPC: G06F9/35

    Abstract: A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset. A multiplexer circuit is coupled to an output of the data pointer register, to an output of the incrementer, and to an output of the adder for selecting a desired indirect addressing mode address.

    7.
    发明专利
    未知

    公开(公告)号：AT224558T

    公开(公告)日：2002-10-15

    申请号：AT98119388

    申请日：1998-10-14

    Applicant: MICROCHIP TECH INC

    Inventor： DRAKE RODNEY J ,  TRIECE JOSEPH W ,  YACH RANDY L ,  BOLES BRIAN ,  WOJEWODA IGOR ,  JOHANSEN DARREL

    IPC: G06F9/35

    Abstract: A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset. A multiplexer circuit is coupled to an output of the data pointer register, to an output of the incrementer, and to an output of the adder for selecting a desired indirect addressing mode address.

    MICROCONTROLLER WITH LOW NOISE PERIPHERAL
    8.
    发明申请
    MICROCONTROLLER WITH LOW NOISE PERIPHERAL 审中-公开
    低噪声外设的微控制器

    公开(公告)号：WO2008014370A3

    公开(公告)日：2008-04-17

    申请号：PCT/US2007074405

    申请日：2007-07-26

    Applicant: MICROCHIP TECH INC ,  WOJEWODA IGOR ,  LOURENS RUAN

    Inventor： WOJEWODA IGOR ,  LOURENS RUAN

    IPC: G06F13/40 ,  H01L23/48

    CPC classification number: G06F13/4072 ,  H01L2224/05554

    Abstract: A microcontroller may have at least a first and second output port coupled with external first and second pins, respectively, a programmable switching arrangement operable in a first mode to provide for a first and second output signal at the first and second pins, respectively, and in a second mode to provide for a first output signal at the first pin and an inverted first output signal at the second pin.

    Abstract translation: 微控制器可以具有至少第一和第二输出端口，分别与外部第一和第二引脚耦合，可编程开关装置可在第一模式下操作以分别在第一和第二引脚处提供第一和第二输出信号，以及 在第二模式中提供第一引脚处的第一输出信号和第二引脚处的反相第一输出信号。

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