MULTIPLE ACCESS METHOD TO SERIAL BUS BY PLURAL CIRCUITS

    公开(公告)号:JPH11120118A

    公开(公告)日:1999-04-30

    申请号:JP21473798

    申请日:1998-06-24

    Abstract: PROBLEM TO BE SOLVED: To enable plural circuit boards to flexibly perform multiple connection to a serial bus. SOLUTION: An original software address must be allocated to each circuit board 12 before the board 12 can be used together with other circuit boards on a common serial bus 18. The original software address is allocated when a bus master device 20 outputs an address allocation command and the command utilizes an original serial number that is stored in each board 12. This address allocation command inquires each board 12 which is connected to the bus 18 and allocates an original software address to each board 12 which responds completely. An address allocation command is repeatedly issued to each board 12 on the bus 18 until the original software address is allocated to all of the boards 12 on the bus 18.

    CONFIGURABLE TIME DELAYS FOR EQUALIZING PULSE WIDTH MODULATION TIMING
    2.
    发明申请
    CONFIGURABLE TIME DELAYS FOR EQUALIZING PULSE WIDTH MODULATION TIMING 审中-公开
    用于均衡脉冲宽度调制时序的可配置时间延迟

    公开(公告)号:WO2014133768A3

    公开(公告)日:2014-10-23

    申请号:PCT/US2014016189

    申请日:2014-02-13

    Abstract: A plurality of PWM generators have user configurable time delay circuits for each PWM control signal generated therefrom. The time delay circuits are adjusted so that each of the PWM control signals arrive at their associated power transistors at the same time. This may be accomplished by determining a maximum delay time of the PWM control signal that has to traverse the longest propagation time and then setting the delay for that PWM control signal to substantially zero delay. Thereafter, all other delay time settings for the other PWM control signals may be determined by subtracting the propagation time for each of the other PWM control signals from the longest propagation time. Thereby insuring that all of the PWM control signals arrive at their respective power transistor control nodes with substantially the same time relationships as when they left their respective PWM generators.

    Abstract translation: 多个PWM发生器具有用于由其产生的每个PWM控制信号的用户可配置时间延迟电路。 延时电路被调整,使得每个PWM控制信号同时到达它们相关的功率晶体管。 这可以通过确定必须经过最长传播时间的PWM控制信号的最大延迟时间,然后将该PWM控制信号的延迟设置为基本为零延迟来实现。 此后,可以通过从最长传播时间中减去每个其他PWM控制信号的传播时间来确定用于其他PWM控制信号的所有其他延迟时间设置。 由此确保所有PWM控制信号以与它们离开它们各自的PWM发生器时基本相同的时间关系到达它们各自的功率晶体管控制节点。

    SYSTEM UND VERFAHREN ZUR RAMPENSTEUERUNG

    公开(公告)号:DE112023003067T5

    公开(公告)日:2025-04-30

    申请号:DE112023003067

    申请日:2023-01-13

    Abstract: Eine Vorrichtung (104) beinhaltet einen Eingang (210) zum Empfangen eines Taktsignals (285), ein Rampen-Start-Programm-Register (220), ein Rampen-Start-Aktiv-Register (260), ein Rampen-Stop-Programm-Register (221), ein Rampen-Stop-Aktiv-Register (261), ein Rampen-Neigung-Programm-Register (222), ein Rampen-Neigungs-Aktiv-Register (262), einen Aktualisierungs-Controller (240), wobei der Aktualisierungs-Controller auf der Grundlage einer programmierbaren Bedingung jeweils den Rampen-Start-Aktiv-Register-Inhalt, den Rampen-Stop-Aktiv-Register-Inhalt und den Rampen-Neigung-Aktiv-Register-Inhalt aktualisiert, und einen Rampen-Controller (280), um ein Rampensignal (290) zu erzeugen, wobei das Rampensignal bei dem Wert beginnt, der den Rampen-Start-Aktiv-Register-Inhalt widerspiegelt, das Rampensignal seinen Wert bei jedem Zyklus des Taktsignals auf der Grundlage des Wertes ändert, der den Rampen-Neigung-Aktiv-Register-Inhalt widerspiegelt, und das Rampensignal bei dem Wert stoppt, der den Rampen-Stop-Aktiv-Register-Inhalt widerspiegelt.

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