Abstract:
PROBLEM TO BE SOLVED: To obtain a lead frame equipping structure in which a contact region between the lead frame mounting structure and an integrated circuit die and to obtain a designing method in which a stress generated by thermal expansion can be dispersed to a bigger region than the die between points with which the lead frame is contacted. SOLUTION: This method in which an integrated circuit die is mounted in a mounting structure contains a step of forming the mounting structure having a die pad and a spreader at least, a step of mounting a contact part on the die pad of the mounting structure and the one spreader at least and a step of the one spreader at least existing between the die pad and the integrated circuit die.
Abstract:
PROBLEM TO BE SOLVED: To function an induction coil as an antenna of a chip by a method wherein a lead frame having a coil structure and an integrated circuit semiconductor chip are combined within a single lead frame package, and the chip is electrically connected to a part of the coil structure of the lead frame. SOLUTION: A package 10 contains a plastic sealing envelope 12, and a lead frame structure 14 of an induction coil shape/structure is housed in the plastic sealing envelope 12. Two terminal pads 26, 28 of an integrated circuit semiconductor chip 24 are connected to an outside end part 30 and an inside end part 32 of an induction coil 14 via conductive wire bonds 34, 36. When the chip 24 is a transmitter type integrated circuit semiconductor chip, generated electric signals are transmitted to the induction coil 14 functioning as a transmission antenna. Furthermore, when the chip 24 is a receiver type integrated circuit semiconductor chip, electric signals are received by the induction coil 14 functioning as a reception antenna.
Abstract:
PROBLEM TO BE SOLVED: To obtain a substrate having excellent deposition and adhesive characteristics of a gold-flash evaporated layer forming an inductive coil by installing the single substrate, the inductive coil placed on one surface of the single substrate and at least one terminal pad electrically connected to at least a part of the inductive coil in a single-sided package. SOLUTION: A gold flash layer having gold in thickness of 7 μ inch is evaporated through a mask, and the coil 10 is formed onto the top face of the substrate 12. The substrate 12 is formed of an epoxy glass plate type material known as an FR4 epoxy glass plate. The chip 14 is mounted on the inside of the inductive coil 10 as the same side as the inductive coil 10 of the substrate 12, and a wire-bonding electrical- connection wiring 18 is formed to sections up to an inductive spot 22 on the substrate 12 from the end section 20 of the outer circumferential turn of the inductive coil 10 and further sections up to the terminal pad 24 of the chip 14 by using a wire bonding technique. Another inductive wire bonding 26 is mounted for connecting the end section 28 of the inner circumferential turn of the inductive coil 10 to the terminal pad 30 of the chip 14.
Abstract:
PROBLEM TO BE SOLVED: To bond an integrated circuit semiconductor chip and a passive element to a single lead frame package, by combining a lead frame arranged in a horizontal plane with the integrated circuit semiconductor chip having terminal pads electrically connected to the coil structure portion of the lead frame. SOLUTION: A package 10 includes a plastic sealing envelope 12 receiving a lead frame structure 14 shaped like an induction coil. The lead frame structure 14 has three tie members 16, for example, which are cut off from the neighboring tie member of a coil-shaped lead frame having the same structure. The tie bar 16 has a function of holding a die paddle in the same plane as a coil 14. Two terminal pads 26, 28 of an integrated circuit semiconductor chip 24 are connected to an outer end portion 30 and an inner end portion 32 of the induction coil 14 by conductive wire bondings 34, 36, respectively.
Abstract:
An integrated device comprises a lead frame having a plurality of inner leads. Furthermore, a first integrated chip is provided that has a plurality of first bond pads for electronically connecting the chip which is attached to the lead frame. A second integrated chip is provided, being smaller than the first chip, and having a plurality of second bond pads. The second chip is attached on top of the first chip. For interconnection, at least one bond wire connects one of the second bond pads of the second chip with one of the first bond pads of the first chip.
Abstract:
Eine Halbleitervorrichtung weist einen Leiterrahmenträger (114, 312, 412, 512) auf, der zum Montieren eines Halbleiterchips (108) ausgebildet ist. Die Halbleitervorrichtung weist weiterhin einen Beschichtungsbereich (304, 404A-404I, 504) auf, der auf dem Leiterrahmenträger (114, 312, 412, 512) ausgebildet ist. Der Beschichtungsbereich (304, 404A-404I, 504) ist so ausgebildet, dass er einen Abwärts verbundenen Verbindungsdraht (110) von einem auf dem Leiterrahmenträger (114, 312, 412, 512) angeordneten Halbleiterchip (108) aufnimmt. Die Halbleitervorrichtung weist weiterhin einen freiliegenden Zwischenraum zwischen einer Außenkante des Beschichtungsbereichs (304, 404A-404I, 504) und einer Außenkante des Leiterrahmenträgers (114, 312, 412, 512) auf.