公开(公告)号：JP2009038806A

公开(公告)日：2009-02-19

申请号：JP2008217229

申请日：2008-08-26

Applicant: Microfabrica Inc ,  マイクロファブリカ インク

Inventor： BROWN ELLIOTT R ,  EVANS JOHN D ,  BANG CHRISTOPHER A ,  COHEN ADAM L ,  LOCKARD MICHAEL S ,  SMALLEY DENNIS R ,  GROSSER MORTON

IPC: H01F41/04 ,  H01P5/22 ,  B81B3/00 ,  C25D1/00 ,  H01F17/00 ,  H01P1/12 ,  H01P1/18 ,  H01P1/202 ,  H01P3/06 ,  H01P5/08 ,  H01P5/16 ,  H01P5/18 ,  H01P7/04 ,  H01P11/00 ,  H01Q3/40 ,  H01Q11/10

CPC classification number: H01P11/005 ,  B81B2201/0292 ,  B81C1/00126 ,  B81C2201/0109 ,  C23C18/1605 ,  C23C18/1651 ,  C25D1/003 ,  H01P1/202 ,  H01P3/06 ,  H01P5/183 ,  H01P11/00

Abstract: PROBLEM TO BE SOLVED: To provide small-sized RF components. SOLUTION: A plurality of components for guiding or controlling RF and microwave radiation are integrated by a plurality of electrodepositions and/or a plurality of laminated materials. The components include a switch, a dielectron an antenna, a transmission line, a filter, a hybrid coupler, an antenna array and/or other active or passive components. The components include a channel that does not allow useful radiated rays to be outputted and input when separating sacrifice materials from composition materials. In a preferred forming process, the electrodeposition mold fabrication technology (e.g., selective deposition, bulk deposition, etching process and flattening process) and post deposition process (e.g., selective etching and/or final backfill process) are employed. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供小尺寸RF组件。 解决方案：用于引导或控制RF和微波辐射的多个部件通过多个电沉积和/或多个层压材料一体化。 组件包括开关，电介质天线，传输线，滤波器，混合耦合器，天线阵列和/或其它有源或无源组件。 这些部件包括在将牺牲材料与组合物材料分离时不允许输出和输入有用辐射光线的通道。 在优选的成形方法中，采用电沉积模制造技术（例如，选择性沉积，本体沉积，蚀刻工艺和压平工艺）和后沉积工艺（例如，选择性蚀刻和/或最终回填工艺）。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：WO2015009874A9

公开(公告)日：2016-04-14

申请号：PCT/US2014046919

申请日：2014-07-16

Applicant: MICROFABRICA INC

Inventor： SCHMITZ GREGORY P ,  LOCKARD MICHAEL S ,  WU MING-TING ,  MILLER ERIC C ,  COHEN ADAM L

IPC: B42D15/00

CPC classification number: B32B15/01 ,  B33Y10/00 ,  B33Y40/00 ,  B33Y70/00 ,  B33Y80/00 ,  C25D1/003 ,  C25D1/08 ,  C25D5/022 ,  C25D5/48 ,  C25D7/005

Abstract: A counterfeiting deterrent device according to one implementation of the disclosure includes a plurality of layers formed by an additive process. Each of the layers may have a thickness of less than 100 microns. At least one of the layers has a series of indentations formed in an outer edge of the layer such that the indentations can be observed to verify that the device originated from a predetermined source. According to another implementation, a counterfeiting deterrent device includes at least one raised layer having outer edges in the shape of a logo. A light source is configured and arranged to shine a light through a slit in a substrate layer of the device and past an intermediate layer to light up the outer edge of the raised layer. The layers of the device are formed by an additive process and have a thickness of less than 100 microns each.

Abstract translation: 根据本公开的一个实施方式的防伪装置包括通过添加过程形成的多个层。 每个层可以具有小于100微米的厚度。 层中的至少一个具有形成在层的外边缘中的一系列凹痕，使得可以观察到凹痕以验证装置源自预定源。 根据另一个实施方案，一种防伪装置包括至少一个具有标志形状的外边缘的凸起层。 光源被配置和布置成将光照射穿过设备的基底层中的狭缝并且经过中间层以照亮凸起层的外边缘。 装置的层通过添加工艺形成，并且具有小于每个100微米的厚度。

公开(公告)号：WO2014113508A3

公开(公告)日：2014-09-12

申请号：PCT/US2014011738

申请日：2014-01-15

Applicant: MICROFABRICA INC

Inventor： VEERAMANI ARUN S ,  JENSEN HEATH A ,  FRODIS URI ,  WIITA CHRISTOPHER G ,  LOCKARD MICHAEL S ,  BOGUSLAVSKY IRINA ,  LEMBRIKOV PAVEL ,  SMALLEY DENNIS R ,  CHEN RICHARD T

IPC: B23K26/36 ,  B23K26/38 ,  B23K26/40 ,  G01R3/00

CPC classification number: B23K26/38 ,  B23K26/0624 ,  B23K26/18 ,  B23K26/40 ,  B23K2201/40 ,  B23K2203/50 ,  G01R1/06738 ,  G01R1/06744 ,  G01R3/00

Abstract: Embodiments are directed to the formation micro-scale or millimeter scale structures or method of making such structures wherein the structures are formed from at least one sheet structural material and may include additional sheet structural materials or deposited structural materials wherein all or a portion of the patterning of the structural materials occurs via laser cutting. In some embodiments, selective deposition is used to provide a portion of the patterning. In some embodiments the structural material or structural materials are bounded from below by a sacrificial bridging material (e.g. a metal) and possibly from above by a sacrificial capping material (e.g. a metal).

Abstract translation: 实施例涉及形成微尺度或毫米级结构或制造这种结构的方法，其中结构由至少一个片状结构材料形成，并且可以包括附加的片状结构材料或沉积的结构材料，其中所有或部分图案化 的结构材料通过激光切割发生。 在一些实施例中，使用选择性沉积来提供图案化的一部分。 在一些实施例中，结构材料或结构材料由牺牲桥接材料（例如金属）从下方限定，并且可能由上面由牺牲性封盖材料（例如金属）限定。

公开(公告)号：WO2004101857A2

公开(公告)日：2004-11-25

申请号：PCT/US2004014360

申请日：2004-05-07

Applicant: MICROFABRICA INC

Inventor： COHEN ADAM L ,  THOMASSIAN JILL R ,  LOCKARD MICHAEL S ,  KILGO MARVIN M III ,  FRODIS URI ,  SMALLEY DENNIS R

IPC: C25D1/00 ,  C25D5/02 ,  C25D5/10 ,  C25D5/14 ,  C25D5/48 ,  C25D5/50 ,  C25D

CPC classification number: C25D1/003 ,  C25D1/00 ,  C25D1/20 ,  C25D5/02 ,  C25D5/022 ,  C25D5/10 ,  C25D5/14 ,  C25D5/48 ,  C25D5/50

Abstract: Numerous electrochemical fabrication methods and apparatus are provided for producing multi-layer structures (e.g. having meso-scale or micro-scale features) from a plurality of layers of deposited materials using adhered masks (e.g. formed from liquid photoresist or dry film), where two or more materials may be provided per layer where at least one of the materials is a structural material and one or more of any other materials may be a sacrificial material which will be removed after formation of the structure. Materials may comprise conductive materials that are electrodeposited or deposited in an electroless manner. In some embodiments special care is undertaken to ensure alignment between patterns formed on successive layers.

Abstract translation: 提供了多种电化学制造方法和装置，用于使用粘附的掩模（例如由液体光致抗蚀剂或干膜形成）从多层沉积材料制备多层结构（例如具有中尺度或微尺度特征），其中两个 或者可以在每层中提供更多的材料，其中至少一种材料是结构材料，并且任何其它材料中的一种或多种可以是在形成结构之后被去除的牺牲材料。 材料可以包括以无电解方式电沉积或沉积的导电材料。 在一些实施例中，特别注意确保在连续层上形成的图案之间的对准。

公开(公告)号：WO2006023696A3

公开(公告)日：2008-11-27

申请号：PCT/US2005029494

申请日：2005-08-19

Applicant: MICROFABRICA INC

Inventor： COHEN ADAM L ,  ARAT VACIT ,  LOCKARD MICHAEL S ,  FOLK CHRISTOPHER R ,  KILGO III MARVIN MOSES

IPC: C25D5/02 ,  C25D5/48 ,  C25D5/52

CPC classification number: H02M7/003 ,  C23C18/1605 ,  C23C18/1651 ,  C25D1/003 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/427 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/0401

Abstract: Embodiments of the invention provide methods for packaging integrated circuits and/or other electronic components with electrochemically fabricated structures which include conductive interconnection elements. In some embodiments the electrochemically produced structures are fabricated on substrates that include conductive vias while in other embodiments, the substrates are solid blocks of conductive material, or conductive material containing passages that allow the flow of fluid to maintain desired thermal properties of the packaged electronic components.

Abstract translation: 本发明的实施例提供了用于封装集成电路和/或具有包括导电互连元件的电化学制造的结构的其它电子部件的方法。 在一些实施例中，电化学产生的结构被制造在包括导电通孔的基板上，而在其他实施例中，基板是导电材料的固体块，或者含有导电材料的通道，其允许流体流动保持封装的电子部件的期望的热性质 。

公开(公告)号：WO2004101856A3

公开(公告)日：2005-07-14

申请号：PCT/US2004014300

申请日：2004-05-07

Applicant: MICROFABRICA INC

Inventor： LOCKARD MICHAEL S ,  SMALLEY DENNIS R ,  LARSEN WILLA M ,  CHEN RICHARD T

IPC: B05D1/32 ,  C23C18/16 ,  C25D5/02 ,  C25D5/10 ,  H01L21/768 ,  C25D5/48 ,  C25D5/52

CPC classification number: C25D1/003 ,  B33Y10/00 ,  C23C18/1605 ,  C23C18/1657 ,  C25D5/022 ,  C25D5/10 ,  H01L21/7682 ,  H01L21/76838

Abstract: Embodiments of the present invention provide mesoscale or microscale three-dimensional structures (e.g. components, device, and the like). Embodiments relate to one or more of (1) the formation of such structures which incorporate sheets of dielectric material and/or wherein seed layer material (1226) used to allow electrodeposition (1228) over dielectric material (1224) is removed via planarization operations; (2) the formation of such structures wherein masks used for at least some selective patterning operations are obtained through transfer plating of masking material to a surface of a substrate or previously formed layer, and/or (3) the formation of such structures wherein masks (1224) used for forming at least portions of some layers are patterned on the build surface directly from data representing the mask configuration, e.g. in some embodiments mask patterning is achieved by selectively dispensing material via a computer controlled inkjet nozzle or array or via a computer controlled extrusion device.

Abstract translation: 本发明的实施例提供中尺度或微尺寸的三维结构（例如部件，装置等）。 实施例涉及以下一个或多个（1）形成这样的结构，其中结合有介电材料片和/或其中通过平面化操作去除用于允许通过电介质材料（1224）的电沉积（1228）的种子层材料（1226） （2）形成这样的结构，其中用于至少一些选择性图案化操作的掩模通过将掩模材料转移到衬底或先前形成的层的表面获得，和/或（3）形成这样的结构，其中掩模 用于形成一些层的至少部分的（1224）直接从表示掩模配置的数据在构建表面上图案化，例如 在一些实施例中，通过经由计算机控制的喷墨喷嘴或阵列或经由计算机控制的挤出装置选择性地分配材料来实现掩模图案化。

公开(公告)号：WO2006031280A3

公开(公告)日：2007-03-01

申请号：PCT/US2005023706

申请日：2005-06-30

Applicant: MICROFABRICA INC ,  KUMAR ANANDA H ,  KRUGLICK EZEKIEL J J ,  COHEN ADAM L ,  KIM KIEUN ,  ZHANG GANG ,  CHEN RICHARD T ,  BANG CHRISTOPHER A ,  ARAT VACIT ,  LOCKARD MICHAEL S ,  FRODIS URI ,  LEMBRIKOV PAVEL B ,  THOMPSON JEFFREY A

Inventor： KUMAR ANANDA H ,  KRUGLICK EZEKIEL J J ,  COHEN ADAM L ,  KIM KIEUN ,  ZHANG GANG ,  CHEN RICHARD T ,  BANG CHRISTOPHER A ,  ARAT VACIT ,  LOCKARD MICHAEL S ,  FRODIS URI ,  LEMBRIKOV PAVEL B ,  THOMPSON JEFFREY A

IPC: G01R31/02

CPC classification number: G01R1/07378 ,  G01R1/06744 ,  G01R3/00 ,  H01L23/66 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/18165 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Embodiments of invention are directed to the formation of microprobes (i.e. compliant electrical or electronic contact elements) on a temporary substrate (306), dicing individual probe arrays (300), and then transferring the arrays to space transformers or other permanent substrates (310). Some embodiments of the invention transfer probes (302) to permanent substrates (310) prior to separating the probes (302) from a temporary substrate (306) on which the probes (302) were formed while other embodiments do the opposite. Some embodiments, remove sacrificial material (308) prior to transfer while other embodiments remove sacrificial material (308) after transfer. Some embodiments are directed to the bonding of first and second electric components together using one or more solder bumps with enhanced aspect ratios (i.e. height to width ratios) obtained as a result of surrounding the bumps at least in part with rings of a retention material. The retention material may act be a solder mask material.

Abstract translation: 本发明的实施例涉及在临时衬底（306）上形成微探针（即柔性电子或电子接触元件），切割各个探针阵列（300），然后将阵列转移到空间变压器或其它永久衬底（310） 。 在将探针（302）与其上形成有探针（302）的临时衬底（306）分离之前，本发明的一些实施例将探针（302）转移到永久衬底（310），而其他实施例相反。 一些实施例，在转移之前去除牺牲材料（308），而其他实施例在转移之后去除牺牲材料（308）。 一些实施例涉及使用一个或多个具有增强的纵横比（即，高度与宽度比）的焊料凸块来将第一和第二电气部件接合在一起，这是由于至少部分地由保持材料的环围绕凸块而得到的。 保留材料可以用作焊接掩模材料。

公开(公告)号：WO2005065436A3

公开(公告)日：2006-04-06

申请号：PCT/US2005000086

申请日：2005-01-03

Applicant: MICROFABRICA INC ,  KUMAR ANANDA H ,  COHEN ADAM L ,  LOCKARD MICHAEL S

Inventor： KUMAR ANANDA H ,  COHEN ADAM L ,  LOCKARD MICHAEL S

IPC: B05D1/38 ,  C08K3/00 ,  C25D3/30 ,  C25D3/38 ,  C25D3/48 ,  C25D5/02 ,  C25D5/10 ,  C25D21/12 ,  H01L21/288 ,  H01L21/301 ,  H01L21/302 ,  H01L21/4763 ,  H01L21/768 ,  B24B53/00

CPC classification number: C25D5/48 ,  B33Y10/00 ,  B81C1/00492 ,  B81C99/0065 ,  B81C2201/0104 ,  B81C2201/0197 ,  C25D1/00 ,  C25D1/003 ,  C25D5/022 ,  C25D5/10 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76885 ,  Y10T156/1052

Abstract: Some embodiments of the present invention provide processes and apparatus for electrochemically fabricating multilayer structures (98) (e.g. mesoscale or microscale structures) with improved endpoint detection and parallelism maintenance for materials (e.g. layers) that are planarized during the electrochemical fabrication process. Some methods involve the use of a fixture during planarization that ensures that planarized planes of material are parallel to other deposited planes within a given tolerance. Some methods involve the use of an endpoint detection fixture (292, 294, 296, 298) that ensures precise heights of deposited materials relative to an initial surface of a substrate (82), relative to a first deposited layer, or relative to some other layer formed during the fabrication process. In some embodiments planarization may occur via lapping while other embodiments may use a diamond fly cutting machine (408).

Abstract translation: 本发明的一些实施例提供了用于电化学制造多层结构（98）（例如中尺度或微结构）的方法和装置，其具有改进的端点检测和在电化学制造过程中被平坦化的材料（例如层）的并行维护。 一些方法涉及在平坦化期间使用夹具，其确保材料的平面化平面平行于给定公差内的其它沉积平面。 一些方法涉及使用端点检测固定装置（292,294,296,298），其相对于第一沉积层相对于衬底（82）的初始表面或相对于某些其它材料确保沉积材料的精确高度 在制造过程中形成的层。 在一些实施例中，平面化可以通过研磨发生，而其他实施例可以使用金刚石切片机（408）。

公开(公告)号：WO2005065430A3

公开(公告)日：2005-11-03

申请号：PCT/US2005000165

申请日：2005-01-03

Applicant: MICROFABRICA INC ,  COHEN ADAM L ,  FRODIS URI ,  LOCKARD MICHAEL S ,  KUMAR ANANDA H ,  ZHANG GANG ,  SMALLEY DENNIS R

Inventor： COHEN ADAM L ,  FRODIS URI ,  LOCKARD MICHAEL S ,  KUMAR ANANDA H ,  ZHANG GANG ,  SMALLEY DENNIS R

IPC: B05D1/38 ,  C08K3/00 ,  C25D3/30 ,  C25D3/38 ,  C25D3/48 ,  C25D5/02 ,  C25D5/10 ,  C25D21/12 ,  H01L21/288 ,  H01L21/301 ,  H01L21/302 ,  H01L21/4763 ,  H01L21/768

CPC classification number: C25D5/48 ,  B33Y10/00 ,  B81C1/00492 ,  B81C99/0065 ,  B81C2201/0104 ,  B81C2201/0197 ,  C25D1/00 ,  C25D1/003 ,  C25D5/022 ,  C25D5/10 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76885 ,  Y10T156/1052

Abstract: Electrochemical fabrication methods for forming single and multilayer mesoscale and microscale structures are disclosed which include the use of diamond machining (e.g. fly cutting or turning) to planarize layers. Some embodiments focus on systems of sacrificial and structural materials which are useful in Electrochemical fabrication and which can be diamond machined with minimal tool wear (e.g. Ni-P and Cu, Au and Cu, Cu and Sn, Au and Cu, Au and Sn, and Au and Sn-Pb), where the first material or materials are the structural materials and the second is the sacrificial material). Some embodiments focus on methods for reducing tool wear when using diamond machining to planarize structures being electrochemically fabricated using difficult-to-machine materials (e.g. by depositing difficult to machine material selectively and potentially with little excess plating thickness, and/or pre-machining depositions to within a small increment of desired surface level (e.g. using lapping or a rough cutting operation) and then using diamond fly cutting to complete the process, and/or forming structures or portions of structures from thin walled regions of hard-to-machine materials as opposed to wide solid regions of structural material.

Abstract translation: 公开了用于形成单层和多层中尺度和微尺度结构的电化学制造方法，其包括使用金刚石机械加工（例如飞切或车削）来平面化层。 一些实施例集中于可用于电化学制造的牺牲和结构材料系统，并且该系统可以以最小的工具磨损进行金刚石加工（例如，Ni-P和Cu，Au和Cu，Cu和Sn，Au和Cu，Au和Sn， 以及Au和Sn-Pb），其中第一种或多种材料是结构材料，第二种是牺牲材料）。 一些实施例集中于减少使用金刚石加工来平坦化使用难加工材料电化学制造的结构时的工具磨损的方法（例如，通过选择性沉积困难的机械材料并且可能几乎没有过量的电镀厚度，和/或预加工沉积 在期望的表面水平的小增量内（例如使用研磨或粗切割操作），然后使用金刚石飞切来完成该过程，和/或从难加工材料的薄壁区域形成结构或部分结构 而不是结构材料的广阔固体区域。

公开(公告)号：EP1711961A4

公开(公告)日：2008-10-22

申请号：EP05704921

申请日：2005-01-03

Applicant: MICROFABRICA INC

Inventor： KUMAR ANANDA H ,  COHEN ADAM L ,  LOCKARD MICHAEL S

IPC: C25D1/00 ,  B05D1/38 ,  B24B49/00 ,  B81C1/00 ,  C08K3/00 ,  C25D3/30 ,  C25D3/38 ,  C25D3/48 ,  C25D5/02 ,  C25D5/10 ,  C25D15/02 ,  C25D21/12 ,  G01B5/06 ,  G01B5/28 ,  H01L21/288 ,  H01L21/301 ,  H01L21/302 ,  H01L21/3105 ,  H01L21/4763 ,  H01L21/768

CPC classification number: C25D5/48 ,  B33Y10/00 ,  B81C1/00492 ,  B81C99/0065 ,  B81C2201/0104 ,  B81C2201/0197 ,  C25D1/00 ,  C25D1/003 ,  C25D5/022 ,  C25D5/10 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76885 ,  Y10T156/1052

Abstract: Some embodiments of the present invention provide processes and apparatus for electrochemically fabricating multilayer structures (98) (e.g. mesoscale or microscale structures) with improved endpoint detection and parallelism maintenance for materials (e.g. layers) that are planarized during the electrochemical fabrication process. Some methods involve the use of a fixture during planarization that ensures that planarized planes of material are parallel to other deposited planes within a given tolerance. Some methods involve the use of an endpoint detection fixture (292, 294, 296, 298) that ensures precise heights of deposited materials relative to an initial surface of a substrate (82), relative to a first deposited layer, or relative to some other layer formed during the fabrication process. In some embodiments planarization may occur via lapping while other embodiments may use a diamond fly cutting machine (408).

Abstract translation: 本发明的一些实施例中用于制造电化学多层结构（E. G.尺度或微米结构）具有改进的终点检测和并行维护材料（E. G.层）没有被在电化学制造工艺平坦化提供的方法和装置。 一些方法涉及平整过程中使用夹具确实保证没有材料的平坦化面给定的公差范围内平行于其他存放图。 一些方法涉及使用终点检测器具的那样沉积的材料相对的保证了精确的高度，以一个基底，相对于第一沉积层，或相对于在制造过程中形成的一些其他层的初始表面上。 在一些实施例中的平坦化可以通过研磨而其它实施例可以使用金刚石飞切机好发。