MEMBRANE PROBING OF CIRCUITS
    1.
    发明申请
    MEMBRANE PROBING OF CIRCUITS 审中-公开
    膜电极探测

    公开(公告)号:WO1996007924A1

    公开(公告)日:1996-03-14

    申请号:PCT/US1995011273

    申请日:1995-09-08

    CPC classification number: G01R1/0735

    Abstract: First and second bumps (9) electrically connected at first and second positions (62, 63) along a conductive run (52) borne by a flexible substrate (10) are respectively oriented for contact with a pad (8) of a die (2) under test and a pad (20) of a tester structure (1). Second (66, 98) and third (68, 100) conductive regions are electrically connected respectively to the power (Vcc) and ground (Vss) terminals of a power source and an electrical device. The second and third regions are spaced from a first conductive region (68, 91) to filter high-frequency noise components from power and ground potentials provided by the power source.

    Abstract translation: 沿着由柔性基板(10)承载的导电线(52)在第一和第二位置(62,63)处电连接的第一和第二凸块(9)分别被定向成与模具(2)的焊盘(8)接触 )和测试器结构(1)的垫(20)。 第二(66,98)和第三(68,100)导电区域分别电连接到电源和电气设备的功率(Vcc)和接地(Vss)端子。 第二和第三区域与第一导电区域(68,91)间隔开以从由电源提供的功率和接地电位滤除高频噪声分量。

    PACKAGING AND INTERCONNECT SYSTEM FOR INTEGRATED CIRCUITS
    2.
    发明申请
    PACKAGING AND INTERCONNECT SYSTEM FOR INTEGRATED CIRCUITS 审中-公开
    集成电路的封装和互连系统

    公开(公告)号:WO1994027318A1

    公开(公告)日:1994-11-24

    申请号:PCT/US1994005172

    申请日:1994-05-10

    Abstract: A thin MCM packaging structure and technique is provided in which a thin decal interconnect circuit (16) is fabricated on a thin aluminum wafer (24). The thin-film decal interconnect (16) employs Au metallurgy for bonding and comprises a bond pad/ground plane layer, topside pads, and one or more routing layers. The top routing layer also acts as the pad layer along the edge of the interconnect structure. The underside of the decal interconnect structure is provided with metal pads for attachment to conventional aluminum or gold I/O pads (60, 62, 64) on one surface of the integrated circuit die (12). A thermosonic bonding system is used to bond the die pads to the pads. The aluminum wafer is selectively removed forming one or more cavities (18) to hold one or more die (12) to be mounted on the MCM structure. The dies (12) are oriented with their pads (60, 62, 64) in contact with contact pads (30, 32, 34) on the thin-film decal interconnect to which they are bonded and the cavities (18) are filled with a liquid encapsulant (26) and cured. The composite structure may be lapped down to minimize overall package thickness and to expose the backsides of the integrated circuit die for thermal management.

    Abstract translation: 提供了一种薄的MCM封装结构和技术,其中在薄铝晶片(24)上制造薄的贴片互连电路(16)。 薄膜贴片互连(16)采用Au冶金用于粘合,并且包括接合焊盘/接地平面层,顶侧焊盘和一个或多个布线层。 顶部路由层还沿着互连结构的边缘充当焊盘层。 贴花互连结构的下侧设置有用于与集成电路管芯(12)的一个表面上的常规铝或金I / O焊盘(60,62,64)连接的金属焊盘。 热键结合系统用于将管芯焊盘焊接到焊盘。 选择性地去除铝晶片形成一个或多个空腔(18)以保持待安装在MCM结构上的一个或多个模具(12)。 模具12被定位成使它们的垫片(60,62,64)与它们所接合的薄膜贴片互连件上的接触焊盘(30,32,34)接触,并且空腔(18)被填充 液体密封剂(26)并固化。 复合结构可以被倒下以最小化整体封装厚度并暴露集成电路管芯的背面用于热管理。

    PROGRAMMABLE HIGH DENSITY ELECTRONIC TESTING DEVICE
    3.
    发明申请
    PROGRAMMABLE HIGH DENSITY ELECTRONIC TESTING DEVICE 审中-公开
    可编程高密度电子测试设备

    公开(公告)号:WO1996013967A1

    公开(公告)日:1996-05-09

    申请号:PCT/US1995013510

    申请日:1995-10-19

    Abstract: A method and an apparatus for routing test signals between pads of a device under test (12) and a tester circuit (20) includes a probe support (64), a substrate (60) with contact points (43), one for each of the pads (13) to be tested, a number of conductors (29) for connection to the tester circuit (20), the number of conductors being fewer than the number of contact points (43) on the substrate (60), and switching circuitry (44a, 44b) mounted on the probe support (64) for routing the test signals between the conductors (29) and the contact points (43).

    Abstract translation: 一种用于在被测设备(12)和测试器电路(20)的焊盘之间布置测试信号的方法和装置包括探针支架(64),具有接触点(43)的衬底(60),每个 要测试的焊盘(13),用于连接到测试器电路(20)的多个导体(29),导体的数量少于衬底(60)上的接触点(43)的数量,并且切换 电路(44a,44b)安装在所述探针支架(64)上,用于在所述导体(29)和所述接触点(43)之间布置所述测试信号。

    PACKAGING AND INTERCONNECT SYSTEM FOR INTEGRATED CIRCUITS
    4.
    发明申请
    PACKAGING AND INTERCONNECT SYSTEM FOR INTEGRATED CIRCUITS 审中-公开
    集成电路的封装和互连系统

    公开(公告)号:WO1997036325A1

    公开(公告)日:1997-10-02

    申请号:PCT/US1997004827

    申请日:1997-03-24

    Abstract: A thin MCM packaging structure (10) and technique is provided in which a thin film decal interconnect circuit (16) is fabricated on a thin aluminum wafer (22). The thin film decal interconnect (16) employs AU metallurgy for bonding and comprises a bond pad/ground plane layer, topside pads, and one or more routing layers. The top routing layer also acts as the pad layer along the edge of the interconnect structure (16). The underside of the decal interconnect structure (16) is provided with metal pads for attachment to conventional aluminum or gold I/O pads on one surface of the integrated circuit die (12). A thermosonic bonding system is used to bond the die pads (66) to the pads. The aluminum wafer is selectively removed forming one or more cavities (18, 20) to hold one or more die (12, 14) to be mounted on the MCM structure (10). The dies (12, 14) are oriented with their pads (66, 70) in contact with contact pads on the thin film decal interconnect (16) to which they are bonded and cavities (18, 20) are filled with a liquid encapsulant (26) and cured. A lead frame has inner bond leads electrically bonded to bonding pads (122) of the thin film multilayer interconnect circuit disposed about periphery thereof and a multilayer laminate board is mechanically bonded over the thin film multilayer interconnect circuit (16) and over the inner bond leads of the lead frame (120) and has a first layer (124) including conductive pads (130) extending outward from about an inner periphery thereof, and a second layer including apertures (136) aligned with outwardly extending portions of the conductive pads (130).

    Abstract translation: 提供了一种薄MCM封装结构(10)和技术,其中在薄铝晶片(22)上制造薄膜贴片互连电路(16)。 薄膜贴片互连(16)采用AU冶金结合,并包括接合焊盘/接地平面层,顶层焊盘和一个或多个布线层。 顶部路由层还沿着互连结构(16)的边缘充当焊盘层。 贴花互连结构(16)的下侧设置有用于附接到集成电路管芯(12)的一个表面上的常规铝或金I / O焊盘的金属焊盘。 使用热超声键合系统将芯片焊盘(66)连接到焊盘。 铝晶片被选择性地移除,形成一个或多个空腔(18,20)以保持要安装在MCM结构(10)上的一个或多个管芯(12,14)。 模具(12,14)被定向成使它们的垫片(66,70)与它们所接合的薄膜贴片互连(16)上的接触焊盘接触,并且空腔(18,20)填充有液体密封剂 26)并固化。 引线框架具有电连接到设置在其周围的薄膜多层互连电路的接合焊盘(122)的内部接合引线,并且多层层压板机械地接合在薄膜多层互连电路(16)上并且在内部接合引线 ,并且具有包括从其内周向外延伸的导电焊盘(130)的第一层(124),以及包括与所述导电焊盘(130)的向外延伸部分对准的孔(136)的第二层 )。

    DUAL-MICROPROCESSOR MODULE HAVING TWO MICROPROCESSORS EACH CAPABLE OF OPERATING IN INDEPENDENT MODE AND COOPERATIVE MODE
    5.
    发明申请
    DUAL-MICROPROCESSOR MODULE HAVING TWO MICROPROCESSORS EACH CAPABLE OF OPERATING IN INDEPENDENT MODE AND COOPERATIVE MODE 审中-公开
    具有独立模式和合作模式操作的两个微处理器的双微处理器模块

    公开(公告)号:WO1996007143A1

    公开(公告)日:1996-03-07

    申请号:PCT/US1995010655

    申请日:1995-08-21

    CPC classification number: G06F13/4068

    Abstract: A dual-microprocessor module (110) includes two microprocessors (112, 112') each of a kind which has two selectable modes of operation, an independent mode in which it can operate independently and a cooperative mode in which it can cooperate with another microprocessor when interconnected in a predefined way with the other microprocessor. Conductors (127) interconnect the microprocessors in the predefined way for operation in the cooperative mode. A housing (114) supports the microprocessors and the conductors. An array of pins (116) are used to mount the module in a socket (120) on a circuit board (126) and the pins are connected to the microprocessors. A socket/circuit board combination includes a socket having an array of holes (118) for receiving pins of a microprocessor package. The holes are connected to runs on the circuit board, the array of holes and the runs being organized to accept either a package containing a single microprocessor or a package containing dual microprocessors interconnected to permit them to operate cooperatively, without requiring rewiring of the circuit board.

    Abstract translation: 双微处理器模块(110)包括两个微处理器(112,112'),每个微处理器具有两种可选择的操作模式,独立模式,其中它可以独立地操作,以及可以与另一微处理器协作的协作模式 当以预定义的方式与另一微处理器互连时。 导体(127)以预定义的方式将微处理器互相连接,以便在协作模式下操作。 壳体(114)支撑微处理器和导体。 引脚阵列(116)用于将模块安装在电路板(126)上的插座(120)中,并且引脚连接到微处理器。 插座/电路板组合包括具有用于接收微处理器封装的引脚的孔阵列(118)的插座。 这些孔连接在电路板上运行,孔阵列和运行被组织以接受包含单个微处理器的封装或者包含互连的双微处理器的封装,以允许它们协同工作,而不需要重新布线电路板 。

    MEMBRANE PROBING OF CIRCUITS
    7.
    发明申请
    MEMBRANE PROBING OF CIRCUITS 审中-公开
    膜电极探测

    公开(公告)号:WO1996007921A1

    公开(公告)日:1996-03-14

    申请号:PCT/US1995011275

    申请日:1995-09-08

    CPC classification number: G01R1/0735

    Abstract: First (46) and second (62, 63) bumps electrically connected at first and second positions along a conductive run (52) borne by a flexible substrate (10) are respectively oriented for contact with a pad (8) of a die under test (2) and a pad (88, 89) of a tester. A probe frame (32) is bonded to the substrate between connector frames (34) bonded at opposite ends of the substrate (10). Alternatively, a pair of bumps (46, and 62, 63) exposed on the same surface of a flexible substrate (10) are electrically connected at different positions along on conductive run (52). One of the bumps (46) is oriented for contact with a pad (8) of a die under test (2), and the other (62, 63) is in contact with a pad (88, 89) on a surface of a printed circuit board (5) directed away from the die (2). The pad (88, 89) of the printed circuit board (5) is provided for electrical connection to a tester.

    Abstract translation: 在沿着由柔性基板(10)承载的导电行程(52)的第一和第二位置电连接的第一(46)和第二(62,63)凸块分别被定向成与被测试的模具的焊盘(8)接触 (2)和测试器的垫(88,89)。 在基板(10)的相对端处接合的连接器框架(34)之间将探针框架(32)接合到基板。 或者,暴露在柔性基板(10)的相同表面上的一对凸块(46,62,63)沿着导电行程(52)在不同位置电连接。 凸块(46)中的一个被定向成与被测试模具(2)的焊盘(8)接触,另一个(62,63)与焊盘(88,89)接触, 印刷电路板(5)远离模具(2)。 印刷电路板(5)的焊盘(88,89)被设置用于与测试仪电连接。

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