Abstract:
First and second bumps (9) electrically connected at first and second positions (62, 63) along a conductive run (52) borne by a flexible substrate (10) are respectively oriented for contact with a pad (8) of a die (2) under test and a pad (20) of a tester structure (1). Second (66, 98) and third (68, 100) conductive regions are electrically connected respectively to the power (Vcc) and ground (Vss) terminals of a power source and an electrical device. The second and third regions are spaced from a first conductive region (68, 91) to filter high-frequency noise components from power and ground potentials provided by the power source.
Abstract:
A thin MCM packaging structure and technique is provided in which a thin decal interconnect circuit (16) is fabricated on a thin aluminum wafer (24). The thin-film decal interconnect (16) employs Au metallurgy for bonding and comprises a bond pad/ground plane layer, topside pads, and one or more routing layers. The top routing layer also acts as the pad layer along the edge of the interconnect structure. The underside of the decal interconnect structure is provided with metal pads for attachment to conventional aluminum or gold I/O pads (60, 62, 64) on one surface of the integrated circuit die (12). A thermosonic bonding system is used to bond the die pads to the pads. The aluminum wafer is selectively removed forming one or more cavities (18) to hold one or more die (12) to be mounted on the MCM structure. The dies (12) are oriented with their pads (60, 62, 64) in contact with contact pads (30, 32, 34) on the thin-film decal interconnect to which they are bonded and the cavities (18) are filled with a liquid encapsulant (26) and cured. The composite structure may be lapped down to minimize overall package thickness and to expose the backsides of the integrated circuit die for thermal management.
Abstract:
A method and an apparatus for routing test signals between pads of a device under test (12) and a tester circuit (20) includes a probe support (64), a substrate (60) with contact points (43), one for each of the pads (13) to be tested, a number of conductors (29) for connection to the tester circuit (20), the number of conductors being fewer than the number of contact points (43) on the substrate (60), and switching circuitry (44a, 44b) mounted on the probe support (64) for routing the test signals between the conductors (29) and the contact points (43).
Abstract:
A thin MCM packaging structure (10) and technique is provided in which a thin film decal interconnect circuit (16) is fabricated on a thin aluminum wafer (22). The thin film decal interconnect (16) employs AU metallurgy for bonding and comprises a bond pad/ground plane layer, topside pads, and one or more routing layers. The top routing layer also acts as the pad layer along the edge of the interconnect structure (16). The underside of the decal interconnect structure (16) is provided with metal pads for attachment to conventional aluminum or gold I/O pads on one surface of the integrated circuit die (12). A thermosonic bonding system is used to bond the die pads (66) to the pads. The aluminum wafer is selectively removed forming one or more cavities (18, 20) to hold one or more die (12, 14) to be mounted on the MCM structure (10). The dies (12, 14) are oriented with their pads (66, 70) in contact with contact pads on the thin film decal interconnect (16) to which they are bonded and cavities (18, 20) are filled with a liquid encapsulant (26) and cured. A lead frame has inner bond leads electrically bonded to bonding pads (122) of the thin film multilayer interconnect circuit disposed about periphery thereof and a multilayer laminate board is mechanically bonded over the thin film multilayer interconnect circuit (16) and over the inner bond leads of the lead frame (120) and has a first layer (124) including conductive pads (130) extending outward from about an inner periphery thereof, and a second layer including apertures (136) aligned with outwardly extending portions of the conductive pads (130).
Abstract:
A mounting assembly for a multiple chip module (13) or other circuit module, which includes a board (11) having a surface including an array of board contacts (22) such as a printed wiring board in a computer system. A circuit module, such as multiple chip module (13), having a first surface and a second surface is included. The circuit module includes an array of circuit contacts (23) on the first surface of the module. An interposer (12) between the board (11) and the first surface of the circuit module, includes conductors (21) between the circuit contacts in the array of circuit contacts (23) on the circuit module and board contacts in the array of board contacts (22) on the board. A thermal bridge member (15) contacts the second surface of the circuit module.
Abstract:
A dual-microprocessor module (110) includes two microprocessors (112, 112') each of a kind which has two selectable modes of operation, an independent mode in which it can operate independently and a cooperative mode in which it can cooperate with another microprocessor when interconnected in a predefined way with the other microprocessor. Conductors (127) interconnect the microprocessors in the predefined way for operation in the cooperative mode. A housing (114) supports the microprocessors and the conductors. An array of pins (116) are used to mount the module in a socket (120) on a circuit board (126) and the pins are connected to the microprocessors. A socket/circuit board combination includes a socket having an array of holes (118) for receiving pins of a microprocessor package. The holes are connected to runs on the circuit board, the array of holes and the runs being organized to accept either a package containing a single microprocessor or a package containing dual microprocessors interconnected to permit them to operate cooperatively, without requiring rewiring of the circuit board.
Abstract:
An assembly for electronic components having heat spreaders (11, 17) on two sides comprises a mother board (13) on which to mount electronic components, having a top side with an array of board contacts. A multiple chip integrated circuit module (16) carries integrated circuits. The multiple chip module consists of a first substrate, such as aluminum, with a multi-layer interconnect structure on one surface of the aluminum substrate. The integrated circuits are mounted on the interconnect structure on the first substrate. A second substrate manufactured using printed wiring board technology, surrounds the first substrate, and includes an interconnect structure and an array of circuit contacts. Conductors connect the interconnect structure on the first substrate with the interconnect structure (31) on the second substrate. A thermally conductive beseplate (32) is coupled with the multiple chip module on the side opposite the array of circuit contacts. An interposer (15) providing electrical connection between the array of circuit contacts on the multiple chip module and the array of board contacts on the printed wiring board is placed between the multiple chip module and the board.
Abstract:
A method for rendering a surface of a contact rough includes submerging the surface of the contact in an electroplating bath (18) having a dissolved metal salt, and pulsing an electric current through the contact and the bath (18) to form a rough metallic structure on the surface of the contact.
Abstract:
First (46) and second (62, 63) bumps electrically connected at first and second positions along a conductive run (52) borne by a flexible substrate (10) are respectively oriented for contact with a pad (8) of a die under test (2) and a pad (88, 89) of a tester. A probe frame (32) is bonded to the substrate between connector frames (34) bonded at opposite ends of the substrate (10). Alternatively, a pair of bumps (46, and 62, 63) exposed on the same surface of a flexible substrate (10) are electrically connected at different positions along on conductive run (52). One of the bumps (46) is oriented for contact with a pad (8) of a die under test (2), and the other (62, 63) is in contact with a pad (88, 89) on a surface of a printed circuit board (5) directed away from the die (2). The pad (88, 89) of the printed circuit board (5) is provided for electrical connection to a tester.
Abstract:
A semiconductor die carrier (10) is provided for testing semiconductor circuits, the carrier (10), containing: a substrate (16) defining an opening and an outer perimeter (16); I/O pads (18) about the perimeter and an interconnect circuit (37) which includes individual electrical conductors formed in a polymer dielectric. The interconnect circuit overlays a top surface of the substrate and extends across the opening to form a flexible membrane (20) that spans the opening. Die contact pads connected to the conductors are disposed about the membrane with particles deposited on the die contact pads. A fence (23) upstanding from the membrane (20) and sized to receive a test die (22); a top cap (12) that rests upon the die when the die is received within the fence, a bottom cap (14) that rests against a bottom surface of the substrate; and a fastener (30) for securing the top cap to the bottom cap with the die in between are also provided.