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    METHOD FOR FORMING AN ELECTRICALLY CONDUCTIVE VIA IN A SUBSTRATE
    1.
    发明申请
    METHOD FOR FORMING AN ELECTRICALLY CONDUCTIVE VIA IN A SUBSTRATE 审中-公开
    通过基板形成电导通的方法

    公开(公告)号：WO2014070017A1

    公开(公告)日：2014-05-08

    申请号：PCT/NL2013/050787

    申请日：2013-11-05

    Applicant: MICRONIT MICROFLUIDICS B.V.

    Inventor： VAN'T OEVER, Ronny ,  BLOM, Marko Theodoor ,  HANEVELD, Jeroen ,  OONK, Johannes ,  TIJSSEN, Peter

    IPC: H01L21/48 ,  H01L23/14 ,  H01L21/683

    CPC classification number: H01L21/76879 ,  B81C1/00095 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/49827 ,  H01L2221/68345 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The invention relates to a method for forming an electrically conductive via in a substrate and such a substrate comprising an electrically conductive, said method comprising the steps, to be performed in suitable sequence, of: a) providing a first substrate as said substrate; b) forming a through hole in said first substrate; c) providing a second substrate; d) bringing a first surface of said second substrate into contact with said first surface of said first substrate, such that said through hole in said first substrate is covered by said first surface of said second substrate; e) filling said through hole in said first substrate with an electrically conductive material by means of electroplating for forming said electrically conductive via, and f) removing said second substrate, wherein said first surface of said first substrate and said first surface of said second substrate each have a surface roughness R a of less than 2nm, preferably less than 1 nm, more preferably less than 0.5 nm, and in that in step (d) said first surface of said first substrate and said first surface of said second substrate are brought in direct contact with each other, such that a direct bond is formed there between.

    Abstract translation: 本发明涉及一种用于在衬底中形成导电通孔的方法，并且这种衬底包括导电的所述方法，所述方法包括以适当顺序执行的以下步骤：a）提供作为所述衬底的第一衬底; b）在所述第一衬底中形成通孔; c）提供第二衬底; d）使所述第二基板的第一表面与所述第一基板的所述第一表面接触，使得所述第一基板中的所述通孔被所述第二基板的所述第一表面覆盖; e）通过用于形成所述导电通孔的电镀用导电材料填充所述第一衬底中的所述通孔，以及f）去除所述第二衬底，其中所述第一衬底的所述第一表面和所述第二衬底的所述第一表面 每个表面粗糙度R a小于2nm，优选小于1nm，更优选小于0.5nm，并且在步骤（d）中，使所述第一基板的所述第一表面和所述第二基板的所述第一表面带入 彼此直接接触，从而在其间形成直接粘结。

    METHODS FOR MANUFACTURING A MICROSTRUCTURE
    3.
    发明申请
    METHODS FOR MANUFACTURING A MICROSTRUCTURE 审中-公开
    制造微结构的方法

    公开(公告)号：WO2009048321A2

    公开(公告)日：2009-04-16

    申请号：PCT/NL2008/000217

    申请日：2008-10-03

    Applicant: MICRONIT MICROFLUIDICS B.V. ,  VAN'T OEVER, Ronny ,  BLOM, Marko, Theodoor ,  OONK, Johannes

    Inventor： VAN'T OEVER, Ronny ,  BLOM, Marko, Theodoor ,  OONK, Johannes

    IPC: B81C1/00

    CPC classification number: B81C1/00119 ,  B81B2203/0376 ,  B81C1/00103 ,  B81C2201/0146

    Abstract: Methods for manufacturing a microstructure, wherein use is made of powder blasting and/or etching and a single mask layer with openings and structures of varying dimensions, characterized in that the mask layer at least at one given point in time has been wholly worn away within at least one region by mask erosion while the microstructure is not yet wholly realized. Use can be made of a combination of 'vertical' erosion, i.e. parallel to the thickness direction, and 'horizontal' erosion, i.e. perpendicularly of the thickness direction, of the mask layer. The horizontal mask erosion occurs at the edges of the mask structure. By selecting the size of the mask openings and the mask structures in a correct manner the mask layer in a region with smaller mask structures will be fully worn away at a given point in time, while in another region with larger structures the mask layer still has sufficient thickness to serve as protection against the powder blasting or etching.

    Abstract translation: 用于制造微结构的方法，其中使用粉末喷射和/或蚀刻以及具有不同尺寸的开口和结构的单个掩模层，其特征在于，所述掩模层至少在一个给定点 随着时间的推移，在至少一个区域内被掩模侵蚀完全磨损，而微观结构尚未完全实现。 可以使用“垂直”侵蚀（即平行于厚度方向）和掩模层的“水平”侵蚀（即垂直于厚度方向）的组合。 水平掩模腐蚀发生在掩模结构的边缘处。 通过以正确的方式选择掩模开口和掩模结构的大小，具有较小掩模结构的区域中的掩模层将在给定时间点完全磨损，而在具有较大结构的另一区域中，掩模层仍然具有 足够的厚度以防止粉末喷射或蚀刻。

    METHODS FOR MANUFACTURING A MICROSTRUCTURE
    5.
    发明公开
    METHODS FOR MANUFACTURING A MICROSTRUCTURE 有权
    一种用于生产微结构

    公开(公告)号：EP2207749A2

    公开(公告)日：2010-07-21

    申请号：EP08838017.5

    申请日：2008-10-03

    Applicant: Micronit Microfluidics B.V.

    Inventor： VAN'T OEVER, Ronny ,  BLOM, Marko, Theodoor ,  OONK, Johannes

    IPC: B81C1/00

    CPC classification number: B81C1/00119 ,  B81B2203/0376 ,  B81C1/00103 ,  B81C2201/0146

    Abstract: Methods for manufacturing a microstructure, wherein use is made of powder blasting and/or etching and a single mask layer with openings and structures of varying dimensions, characterized in that the mask layer at least at one given point in time has been wholly worn away within at least one region by mask erosion while the microstructure is not yet wholly realized. Use can be made of a combination of 'vertical' erosion, i.e. parallel to the thickness direction, and 'horizontal' erosion, i.e. perpendicularly of the thickness direction, of the mask layer. The horizontal mask erosion occurs at the edges of the mask structure. By selecting the size of the mask openings and the mask structures in a correct manner the mask layer in a region with smaller mask structures will be fully worn away at a given point in time, while in another region with larger structures the mask layer still has sufficient thickness to serve as protection against the powder blasting or etching.

    METHOD FOR FORMING AN ELECTRICALLY CONDUCTIVE VIA IN A SUBSTRATE
    6.
    发明公开
    METHOD FOR FORMING AN ELECTRICALLY CONDUCTIVE VIA IN A SUBSTRATE 审中-公开
    VERFAHREN ZUR HERSTELLUNG EINES ELEKTRISCH LEITENDEN DURCHGANGS BEI EINEM SUBSTRAT

    公开(公告)号：EP2915188A1

    公开(公告)日：2015-09-09

    申请号：EP13801864.3

    申请日：2013-11-05

    Applicant: Micronit Microfluidics B.V.

    Inventor： VAN'T OEVER, Ronny ,  BLOM, Marko Theodoor ,  HANEVELD, Jeroen ,  OONK, Johannes ,  TIJSSEN, Peter

    IPC: H01L21/48 ,  H01L23/14 ,  H01L21/683

    Abstract: A method for forming an electrically conductive via in a substrate that includes the steps of: forming a through hole in a first substrate; bringing a first surface of a second substrate into contact with the first surface of the first substrate, such that the through hole in the first substrate is covered by the first surface of the second substrate; filling the through hole in the first substrate with an electrically conductive material by electroplating to form the electrically conductive via, and removing the second substrate, wherein the first surface of the first and the second substrate each have a surface roughness Ra of less than 2 nm, preferably less than 1 nm, more preferably less than 0.5 nm, and the first surface of the first and the second substrate are brought in direct contact with each other, such that a direct bond is formed there between.

    Abstract translation: 本发明涉及一种用于在衬底中形成导电通孔的方法，并且这种衬底包括导电的方法，所述方法包括以适当顺序执行的步骤：a）提供作为所述衬底的第一衬底; b）在所述第一衬底中形成通孔; c）提供第二基底; d）使所述第二基板的第一表面与所述第一基板的所述第一表面接触，使得所述第一基板中的所述通孔被所述第二基板的所述第一表面覆盖; e）通过用于形成所述导电通孔的电镀用导电材料填充所述第一衬底中的所述通孔，以及f）去除所述第二衬底，其中所述第一衬底的所述第一表面和所述第二衬底的所述第一表面 每个表面粗糙度R a小于2nm，优选小于1nm，更优选小于0.5nm，并且在步骤（d）中，所述第一衬底的所述第一表面和所述第二衬底的所述第一表面是 导致彼此直接接触，从而在其间形成直接粘结。

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