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    EVEN PROCESS
    3.
    发明专利
    EVEN PROCESS 失效

    公开(公告)号：JPH07307339A

    公开(公告)日：1995-11-21

    申请号：JP8235395

    申请日：1995-04-07

    Applicant: ST MICROELECTRONICS SRL

    Inventor： LOSAVIO ALDO ,  BACCHETTA MAURIZIO

    IPC: H01L21/8247 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L29/788 ,  H01L29/792

    Abstract: PURPOSE: To provide an insulating film which has a highly flat surface without needing heat treatment at high temperature, by forming a barrier layer of an undoped oxide substance on a semiconductor substrate, and stacking an oxide layer in higher phosphorus concentration than boron concentration, and further, heat-treating it after formation of an oxide layer including boron. CONSTITUTION: The first undoped oxide layer (barrier layer) 12 is stacked all over the surface of an integrated circuit by CVD technique. Thereon, the second oxide layer 13 is stacked, using CVD technique, and at this time, the concentration of phosphor for doping is made higher than the concentration of boron. Furthermore, thereon the third oxide layer 14 is stacked by CVD technique, and the concentration of phosphor for doping within this layer is made over the concentration of phosphor, and the fusing-point temperature is selected to drop to a desired value. Lastly, heat treatment is performed to reflow the third oxide layer 14, whereby the surface of the integrated circuit is flattened. As a result, a highly flat insulating film can be obtained without needing heat treatment at high temperature.

    4.
    发明专利
    未知

    公开(公告)号：DE69417211D1

    公开(公告)日：1999-04-22

    申请号：DE69417211

    申请日：1994-04-12

    Applicant: ST MICROELECTRONICS SRL

    Inventor： LOSAVIO ALDO ,  BACCHETTA MAURIZIO

    IPC: H01L21/8247 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L29/788 ,  H01L29/792

    Abstract: A planarization process for the manufacturing of integrated circuits, particularly for non-volatile semiconductor memory devices, comprises the steps of: forming a first layer (12) of undoped oxide acting as a barrier layer over a semiconductor substrate (3) wherein integrated devices (M,MC1,MC2) have been previously obtained; forming a second layer (13) of oxide containing phosphor over the first undoped oxide; forming a third layer (14) of oxide containing phosphor and boron over the second oxide layer, the concentration of phosphor being lower than or equal to the concentration of boron; performing a thermal process at a temperature sufficient to melt the third oxide layer (14), to obtain a planar surface.

    5.
    发明专利
    未知

    公开(公告)号：DE60230592D1

    公开(公告)日：2009-02-12

    申请号：DE60230592

    申请日：2002-05-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  LOSAVIO ALDO

    IPC: G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G11C29/44

    Abstract: The memory device (20) has a memory block (1), formed by a plurality of standard sectors (15) and a redundancy portion (2); a control circuit (3), which controls programming and erasing of the data of the memory cells; and a correctness verifying circuit (7) for the data stored in the memory cells. The correctness verifying circuit (7) is enabled by the control circuit (3) and generates an incorrect-datum signal in the event of detection of at least one non-functioning cell. The control circuit moreover activates redundancy, enabling the redundancy portion (2) and storing redundancy data in a redundancy-memory stage (5b) in the presence of an incorrect datum. Various solutions are presented that implement column, row and sector redundancy, both in case of erasing and programming.

    6.
    发明专利
    未知

    公开(公告)号：DE60212332T2

    公开(公告)日：2007-06-06

    申请号：DE60212332

    申请日：2002-04-26

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  LOSAVIO ALDO

    IPC: G11C29/00

    Abstract: The self-repair method for a nonvolatile memory (1) intervenes at the end of an operation of modification, selected between programming and erasing, in the event of detection of just one non-functioning cell (14a, 14c), and carries out redundancy of the non-functioning cell. To this end, the memory array (15) is divided into a basic portion (20), formed by a plurality of memory cells (14a) storing basic data, and into a on-the-field redundancy portion (21), said on-the-field redundancy portion (21) being designed to store redundancy data including a correct content of the non-functioning cell, the address of the non-functioning cell, and an activated redundancy flag. The redundancy is activated only after applying a preset maximum number of modification pulses and uses a purposely designed redundancy replacement circuit (12) and a purposely designed redundancy data verification circuit (7b).

    9.
    发明专利
    未知

    公开(公告)号：DE60212332D1

    公开(公告)日：2006-07-27

    申请号：DE60212332

    申请日：2002-04-26

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  LOSAVIO ALDO

    IPC: G11C29/00

    Abstract: The self-repair method for a nonvolatile memory (1) intervenes at the end of an operation of modification, selected between programming and erasing, in the event of detection of just one non-functioning cell (14a, 14c), and carries out redundancy of the non-functioning cell. To this end, the memory array (15) is divided into a basic portion (20), formed by a plurality of memory cells (14a) storing basic data, and into a on-the-field redundancy portion (21), said on-the-field redundancy portion (21) being designed to store redundancy data including a correct content of the non-functioning cell, the address of the non-functioning cell, and an activated redundancy flag. The redundancy is activated only after applying a preset maximum number of modification pulses and uses a purposely designed redundancy replacement circuit (12) and a purposely designed redundancy data verification circuit (7b).

    10.
    发明专利
    未知

    公开(公告)号：IT1305829B1

    公开(公告)日：2001-05-16

    申请号：ITVA980012

    申请日：1998-06-05

    Applicant: ST MICROELECTRONICS SRL

    Inventor： LOSAVIO ALDO

    IPC: H01L21/762

    Abstract: A method for recovering the original properties of a silicon oxide film that has suffered a high energy implantation of dopants in the underlying silicon substrate, includes a brief heat treatment without causing an excessive lateral diffusion in the silicon substrate of the implanted dopants. Heat treating in an oven at a temperature of 800° C. for few minutes per wafer, which was subjected to high energy implantation, makes it possible to recover etch rate characteristics that are practically similar to those of the original non-implanted silicon oxide.

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