公开(公告)号：AU2003265969A1

公开(公告)日：2004-04-30

申请号：AU2003265969

申请日：2003-09-05

Applicant: MOTOROLA INC

Inventor： DANVIR JANICE ,  HAN ZHAOJIN ,  KULKARNI PRASANNA ,  YALA NADIA ,  DOOT ROBERT ,  QI JING

IPC: H01L21/60 ,  H01L21/66 ,  H01L23/544 ,  H05K1/02 ,  H05K3/34 ,  H01L31/072 ,  H01L31/109

Abstract: A bumped semiconductor device (10) exhibiting enhanced pattern recognition when illuminated in a machine vision system. The semiconductor device has a substantially coplanar array of solder bumps (16) and a coating of underfill material (17) on one face. A fluxing composition (18) containing an image enhancing agent is selectively deposited over at least two of the solder bumps in the array to modify the optical characteristics of the solder bumps to cause the solder bumps to appear bright against the background of the underfill material when the semiconductor device is illuminated (19) by selected wavelengths of light.

公开(公告)号：MY136290A

公开(公告)日：2008-09-30

申请号：MYPI20041116

申请日：2004-03-29

Applicant: MOTOROLA INC

Inventor： QI JING ,  DANVIR JANICE M ,  KLOSOWIAK TOMASZ L ,  KULKARNI JING ,  NADIA YALA

IPC: H01L21/56

Abstract: THE INVENTION PROVIDES A METHOD FOR ATTACHING A FLIP CHIP (210) TO AN ELECTRICAL SUBSTRATE (240) SUCH AS A PRINTED WIRING BOARD. A BUMPED FLIP CHIP IS PROVIDED, THE FLIP CHIP INCLUDING AN ACTIVE SURFACE AND A PLURALITY OF CONNECTIVE BUMPS (220) EXTENDING FROM THE ACTIVE SURFACE, EACH CONNECTIVE BUMP INCLUDING A SIDE REGION. A THIN LAYER OF AN UNDERFILL MATERIAL (230) IS APPLIED TO THE ACTIVE SURFACE OF THE FLIP CHIP AND TO A PORTION OF THE SIDE REGIONS OF THE CONNECTIVE BUMPS. THE FLIP CHIP IS POSITIONED ON THE ELECTRICAL SUBSTRATE, THE ELECTRICAL SUBSTRATE INCLUDING A THICK LAYER OF A SOLDER MASK (250) DISPOSED ON THE ELECTRICAL SUBSTRATE. THE FLIP CHIP IS HEATED TO ELECTRICALLY CONNECT THE FLIP CHIP TO THE ELECTRICAL SUBSTRATE, WHEREIN THE UNDERFILL MATERIAL AND THE SOLDER MASK COMBINE TO FORM A STRESS-RELIEF LAYER WHEN THE FLIP CHIP IS ELECTRICALLY CONNECTED TO THE ELECTRICAL SUBSTRATE.

公开(公告)号：AU2003296904A1

公开(公告)日：2004-05-04

申请号：AU2003296904

申请日：2003-09-05

Applicant: MOTOROLA INC

Inventor： QI JING ,  DANVIR JANICE ,  KLOSOWIAK TOMASZ

IPC: H01L21/60 ,  H01L21/301 ,  H01L21/304 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31

Abstract: A method for providing an underfill material on an integrated circuit chip at the wafer level. The wafer (10) typically contains one or more integrated circuit chips (12), and each integrated circuit chip typically has a plurality of solder bumps (34) on its active surface. The wafer is first diced (22) on the active surface side to form channels (38) that will ultimately define the edges (39) of each individual integrated circuit chip, the dicing being of such a depth that it only cuts part-way through the wafer. The front side (36) of the wafer is then coated (24) with an underfill material (40). Generally, a portion (45) of each solder bump remains uncoated, but in certain cases the bumps can be completely covered. The back side of the wafer is then lapped, ground, polished or otherwise treated (26) so as to remove material down to the level of the previously diced channels. This reduction in the thickness of the wafer causes the original diced channels to now extend completely from the front side to the back side of the wafer. The wafer is then singulated (28) by cutting the underfill material (92) that was deposited in the channels during the coating step, so that the integrated circuit chip (12) is released from the wafer, and the underfill material that was coated on the active side remains affixed to the active surface of each individual integrated circuit chip.

公开(公告)号：AU2002359885A1

公开(公告)日：2003-07-30

申请号：AU2002359885

申请日：2002-12-31

Applicant: MOTOROLA INC

Inventor： CHASON MARC ,  DANVIR JANICE ,  QI JING ,  YALA NADIA

IPC: H01L21/56 ,  H01L23/31 ,  H05K3/34