公开(公告)号：JP2003216198A

公开(公告)日：2003-07-30

申请号：JP2003006296

申请日：2003-01-14

Applicant: QUALCOMM INC

Inventor： MCDONOUGH JOHN G ,  CHANG CHIENCHUNG ,  SINGH RANDEEP ,  SAKAMAKI CHARLES E ,  TSAI MING-CHANG ,  KANTAK PRASHANT

IPC: G10L19/08 ,  G06F5/01 ,  G10L19/00 ,  G10L19/04 ,  G10L19/06 ,  G10L19/12 ,  G10L19/14 ,  H03M7/30 ,  G10L19/02

Abstract: PROBLEM TO BE SOLVED: To provide a vocoder ASIC (application specific integrated circuit). SOLUTION: A method and apparatus to be used for the vocoder constituted in an application specific integrated circuit (ASIC) is disclosed. The apparatus contains a DSP core (4) that performs computations in accordance with a reduced instruction set (RISC) architecture. The circuit further includes a specifically designed slave processor referred to as the minimization processor (6). The apparatus further comprises a specifically designed normalization circuitry. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2010282637A

公开(公告)日：2010-12-16

申请号：JP2010157075

申请日：2010-07-09

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： SIH GILBERT C ,  ZOU QUIZHEN ,  JHA SANJAY K ,  KANG INYUP ,  LIN JIAN ,  MOTIWALA QUAEED ,  JOHN DEEPU ,  ZHANG LI ,  ZHANG HAITAO ,  LEE WAY-SHING ,  SAKAMAKI CHARLES E ,  KANTAK PRASHANT A

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F13/16 ,  G06F15/78

CPC classification number: G06F12/0886 ,  G06F9/30036 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30141 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3885 ,  G06F9/3893 ,  G06F15/7807

Abstract: PROBLEM TO BE SOLVED: To provide a digital signal processor which enhances performance and availability. SOLUTION: A DSP includes a set of three data buses over which data may be exchanged with a register bank 120 and three data memories 102, 103 and 104. The register bank 120 may be used that includes registers accessible by at least two processing units 128 and 130. An instruction fetch unit 156 may include that receives instructions of variable length stored in an instruction memory 152. The instruction memory 152 may be separated from the set of three data memories 102, 103 and 104. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种提高性能和可用性的数字信号处理器。 解决方案：DSP包括一组三条数据总线，数据可以通过该组三个数据总线与寄存器组120和三个数据存储器102,103和104进行交换。可以使用寄存器组120，其包括可由至少两个 处理单元128和130.指令提取单元156可以包括接收存储在指令存储器152中的可变长度的指令。指令存储器152可以与三组数据存储器102,103和104分离。 ：（C）2011，JPO＆INPIT

公开(公告)号：SG151304A1

公开(公告)日：2009-04-30

申请号：SG2009020108

申请日：2005-03-11

Applicant: QUALCOMM INC

Inventor： SIH GILBERT CHRISTOPHER ,  SAKAMAKI CHARLES E ,  HSU DE D ,  WEI JIAN ,  HIGGINS RICHARD

IPC: G06F12/08

Abstract: CACHED MEMORY SYSTEM AND CACHE CONTROLLER FOR EMBEDDED DIGITAL SIGNAL PROCESSOR A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.

公开(公告)号：AT297567T

公开(公告)日：2005-06-15

申请号：AT99911150

申请日：1999-03-04

Applicant: QUALCOMM INC

Inventor： SIH GILBERT C ,  ZOU QUIZHEN ,  JHA SANJAY K ,  KANG INYUP ,  LIN JIAN ,  MOTIWALA QUAEED ,  JOHN DEEPU ,  ZHANG LI ,  ZHANG HAITAO ,  LEE WAY-SHING ,  SAKAMAKI CHARLES E ,  KANTAK PRASHANT A

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/0886 ,  G06F15/78

Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).

公开(公告)号：ES2130733T3

公开(公告)日：1999-07-01

申请号：ES96117242

申请日：1995-02-13

Applicant: QUALCOMM INC

Inventor： MCDONOUGH JOHN G ,  CHANG CHIENCHUNG ,  SINGH RANDEEP ,  SAKAMAKI CHARLES E ,  TSAI MING-CHANG ,  KANTAK PRASHANT

IPC: G06F5/01 ,  G10L19/00 ,  G10L19/08 ,  G10L19/04 ,  G10L19/06 ,  G10L19/12 ,  G10L19/14 ,  H03M7/30

Abstract: A method and apparatus for implementing a vocoder in an application specific integrated circuit (ASIC) is disclosed. The apparatus contains a DSP core (4) that performs computations in accordance with a reduced instruction set (RISC) architecture. The circuit further comprises a specifically designed slave processor to the DSP core (4) referred to as the minimization processor (6). The feature of the invention is a specifically designed block normalization circuitry.

公开(公告)号：FI20070887A

公开(公告)日：2007-11-21

申请号：FI20070887

申请日：2007-11-21

Applicant: QUALCOMM INC

Inventor： MCDONOUGH JOHN G ,  CHIENCHUNG CHANG ,  RANDEEP SINGH ,  SAKAMAKI CHARLES E ,  TSAI MING-CHANG ,  KANTAK PRASHANT

IPC: G06F5/01 ,  G10L19/08 ,  G10L19/00 ,  G10L19/04 ,  G10L19/06 ,  G10L19/12 ,  G10L19/14 ,  H03M7/30

Abstract: A method and apparatus for implementing a vocoder in an application specific integrated circuit (ASIC) is disclosed. The apparatus contains a DSP core (4) that performs computations in accordance with a reduced instruction set (RISC) architecture. The circuit further comprises a specifically designed slave processor to the DSP core (4) referred to as the minimization processor (6). The feature of the invention is a specifically designed block normalization circuitry.

公开(公告)号：CA2158660C

公开(公告)日：2006-01-24

申请号：CA2158660

申请日：1995-02-13

Applicant: QUALCOMM INC

Inventor： MCDONOUGH JOHN G ,  CHANG CHIENCHUNG ,  SINGH RANDEEP ,  SAKAMAKI CHARLES E ,  TSAI MING-CHANG ,  KANTAK PRASHANT

IPC: G10L19/08 ,  G10L19/14 ,  G06F5/01 ,  G10L19/00 ,  G10L19/04 ,  G10L19/06 ,  G10L19/12 ,  H03M7/30

Abstract: A method and apparatus for implementing a vocoder in an application specific integrated circuit (ASIC) is disclosed. The apparatus contains a DSP core (4 ) that performs computations in accordance with a reduced instruction set (RIS C) architecture. The circuit further comprises a specifically designed slave processor to the DSP core (4) referred to as the minimization processor (6). The apparatus further comprises a specifically designed block normalization circuitry.

公开(公告)号：DK0758123T3

公开(公告)日：1999-11-08

申请号：DK96117242

申请日：1995-02-13

Applicant: QUALCOMM INC

Inventor： MCDONOUGH JOHN G ,  CHANG CHIENCHUNG ,  SINGH RANDEEP ,  SAKAMAKI CHARLES E ,  TSAI MING-CHANG ,  KANTAK PRASHANT

IPC: G06F5/01 ,  G10L19/00 ,  G10L19/04 ,  G10L19/08 ,  G10L19/06 ,  G10L19/12 ,  G10L19/14 ,  H03M7/30 ,  G10L9/14 ,  G10L9/18

Abstract: A method and apparatus for implementing a vocoder in an application specific integrated circuit (ASIC) is disclosed. The apparatus contains a DSP core (4) that performs computations in accordance with a reduced instruction set (RISC) architecture. The circuit further comprises a specifically designed slave processor to the DSP core (4) referred to as the minimization processor (6). The feature of the invention is a specifically designed block normalization circuitry.

公开(公告)号：GR3030467T3

公开(公告)日：1999-10-29

申请号：GR990401540

申请日：1999-06-09

Applicant: QUALCOMM INC

Inventor： MCDONOUGH JOHN G ,  CHANG CHIENCHUNG ,  SINGH RANDEEP ,  SAKAMAKI CHARLES E ,  TSAI MING-CHANG ,  KANTAK PRASHANT

IPC: G06F5/01 ,  G10L19/00 ,  G10L19/06 ,  G10L9/14 ,  G10L9/18

公开(公告)号：AU1846595A

公开(公告)日：1995-09-04

申请号：AU1846595

申请日：1995-02-13

Applicant: QUALCOMM INC

Inventor： MCDONOUGH JOHN G ,  CHANG CHIENCHUNG ,  SINGH RANDEEP ,  SAKAMAKI CHARLES E ,  TSAI MING-CHANG ,  KANTAK PRASHANT

IPC: G10L19/08 ,  G06F5/01 ,  G10L19/00 ,  G10L19/04 ,  G10L19/06 ,  G10L19/12 ,  G10L19/14 ,  H03M7/30 ,  G10L9/14 ,  G10L9/18

Abstract: A method and apparatus for implementing a vocoder in an application specific integrated circuit (ASIC) is disclosed. The apparatus contains a DSP core (4) that performs computations in accordance with a reduced instruction set (RISC) architecture. The circuit further comprises a specifically designed slave processor to the DSP core (4) referred to as the minimization processor (6). The feature of the invention is a specifically designed block normalization circuitry.