公开(公告)号：AU2017217375A1

公开(公告)日：2018-07-26

申请号：AU2017217375

申请日：2017-02-07

Applicant: QUALCOMM INC

Inventor： WE HONG BOK ,  LEE JAE SIK ,  KIM DONG WOOK

IPC: H01L23/538

Abstract: Some features pertain to an integrated device that includes a first integrated circuit (IC) package, a flexible connector and a second integrated circuit (IC) package. The first integrated circuit (IC) package includes a first die, a plurality of first interconnects, and a first dielectric layer encapsulating the first die. The flexible connector is coupled to the first integrated circuit (IC) package. The flexible connector includes the first dielectric layer, and an interconnect. The second integrated circuit (IC) package is coupled to the flexible connector. The second integrated circuit (IC) package includes the first dielectric layer, and a plurality of second interconnects. The first integrated circuit (IC) package, the second integrated circuit (IC) package, and the flexible connector are coupled together through at least a portion (e.g., contiguous portion) of the first dielectric layer. In some implementations, the flexible connector comprises a dummy metal layer.

公开(公告)号：CA2990470A1

公开(公告)日：2017-02-02

申请号：CA2990470

申请日：2016-07-28

Applicant: QUALCOMM INC

Inventor： WE HONG BOK ,  LEE JAE SIK ,  KIM DONG WOOK ,  GU SHIQUN

IPC: H01L21/60 ,  H01L21/56 ,  H01L23/13 ,  H01L23/498 ,  H01L23/538

Abstract: A package-on-package (POP) structure is disclosed. The POP structure includes a first die (116), a second die (156), and a photo-imaged dielectric (PID) layer (124). The PID layer is disposed between the first die and the second die. The POP structure also includes a first conductive path (162,182) from the first die through the PID layer to the second die. The first conductive path extends directly through a first area of the PID layer directly between the first die and the second die. The POP structure further includes a second conductive path (103) from the first die through the PID layer to the second die. A particular portion (113) of the second conductive path is perpendicular to the first conductive path and extends through a second area of the PID layer not directly between the first die and the second die.

公开(公告)号：ES2791881T3

公开(公告)日：2020-11-06

申请号：ES15725963

申请日：2015-05-18

Applicant: QUALCOMM INC

Inventor： WE HONG BOK ,  HWANG KYU-PYUNG ,  SONG YOUNG KYU ,  KIM DONG WOOK

IPC: H01L23/498 ,  H01L23/50

Abstract: Un sustrato de encapsulado (200), que comprende: un sustrato (202) que comprende un primer lado; un condensador (250) incrustado en el sustrato, donde el condensador comprende un primer electrodo (252) y un segundo electrodo (254); una primera placa metálica (224) que se extiende lateralmente en el sustrato, en donde la primera placa metálica está dispuesta directamente sobre el primer electrodo del condensador y se extiende lateralmente desde un primer lado del primer electrodo; y una pluralidad de vías (266), que incluyen una primera vía, que se extiende perpendicularmente hacia la primera placa metálica y se conecta a la primera placa metálica desde el primer lado del sustrato.

公开(公告)号：AU2015287804A1

公开(公告)日：2017-01-05

申请号：AU2015287804

申请日：2015-07-09

Applicant: QUALCOMM INC

Inventor： KIM DONG WOOK ,  SONG YOUNG KYU ,  HWANG KYU-PYUNG ,  WE HONG BOK

IPC: H01L23/498 ,  H01L21/48

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first interconnect coupled to the substrate, and a second interconnect surrounding the first interconnect. The second interconnect may be configured to provide an electrical connection to ground. In some implementations, the second interconnect includes a plate. In some implementations, the integrated device also includes a dielectric material between the first interconnect and the second interconnect. In some implementations, the integrated device also includes a mold surrounding the second interconnect. In some implementations, the first interconnect is configured to conduct a power signal in a first direction. In some implementations, the second interconnect is configured to conduct a grounding signal in a second direction. In some implementations, the second direction is different from the first direction. In some implementations, the integrated device may be a package-on-package (PoP) device.

公开(公告)号：HUE049086T2

公开(公告)日：2020-09-28

申请号：HUE15725963

申请日：2015-05-18

Applicant: QUALCOMM INC

Inventor： WE HONG BOK ,  HWANG KYU-PYUNG ,  SONG YOUNG KYU ,  KIM DONG WOOK

IPC: H01L23/50

公开(公告)号：SG11201701990SA

公开(公告)日：2017-05-30

申请号：SG11201701990S

申请日：2015-09-04

Applicant: QUALCOMM INC

Inventor： KIM DONG WOOK ,  WE HONG BOK ,  LEE JAE SIK ,  GU SHIQUN

IPC: H01L23/498

Abstract: A high density fan out package structure may include a contact layer. The contact layer includes a conductive interconnect layer having a first surface facing an active die and a second surface facing a redistribution layer. The high density fan out package structure has a barrier layer on the first surface of the conductive interconnect layer. The high density fan out package structure may also include the redistribution layer, which has conductive routing layers. The conductive routing layers may be configured to couple a first conductive interconnect to the conductive interconnect layer. The high density fan out package structure may further include a first via coupled to the barrier liner and configured to couple with a second conductive interconnect to the active die.

公开(公告)号：AU2015287804B2

公开(公告)日：2020-02-27

申请号：AU2015287804

申请日：2015-07-09

Applicant: QUALCOMM INC

Inventor： KIM DONG WOOK ,  SONG YOUNG KYU ,  HWANG KYU-PYUNG ,  WE HONG BOK

IPC: H01L23/498 ,  H01L21/48

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first interconnect coupled to the substrate, and a second interconnect surrounding the first interconnect. The second interconnect may be configured to provide an electrical connection to ground. In some implementations, the second interconnect includes a plate. In some implementations, the integrated device also includes a dielectric material between the first interconnect and the second interconnect. In some implementations, the integrated device also includes a mold surrounding the second interconnect. In some implementations, the first interconnect is configured to conduct a power signal in a first direction. In some implementations, the second interconnect is configured to conduct a grounding signal in a second direction. In some implementations, the second direction is different from the first direction. In some implementations, the integrated device may be a package-on-package (PoP) device.

公开(公告)号：CA2991933A1

公开(公告)日：2017-03-02

申请号：CA2991933

申请日：2016-06-03

Applicant: QUALCOMM INC

Inventor： GU SHIQUN ,  WE HONG BOK ,  LEE JAE SIK ,  KIM DONG WOOK

IPC: H01L23/538

Abstract: An integrated device package includes a first die, a second die, an encapsulation portion coupled to the first die and the second die, and a redistribution portion coupled to the encapsulation portion. The encapsulation portion includes an encapsulation layer, a bridge, and a first via. The bridge is at least partially embedded in the encapsulation layer. The bridge is configured to provide a first electrical path for a first signal between the first die and the second die. The first via is in the encapsulation layer. The first via is coupled to the bridge. The first via and the bridge are configured to provide a second electrical path for a second signal to the first die. The redistribution portion includes at least one dielectric layer, and at least one interconnect, in the dielectric layer, coupled to the first via.

公开(公告)号：WO2015160671A9

公开(公告)日：2016-06-09

申请号：PCT/US2015025435

申请日：2015-04-10

Applicant: QUALCOMM INC

Inventor： WE HONG BOK ,  KIM CHIN-KWAN ,  KIM DONG WOOK ,  LEE JAE SIK ,  HWANG KYU-PYUNG ,  SONG YOUNG KYU

IPC: H01L23/528 ,  H01L21/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L21/768 ,  H01L21/4857 ,  H01L21/76802 ,  H01L21/76838 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/49822 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/014

Abstract: An integrated circuit (IC) substrate that includes a second patterned metal layer formed in between a first patterned metal layer is disclosed. A dielectric layer formed on the first patterned metal layer separates the two metal layers. A non-conductive layer is formed on the dielectric layer and the second patterned metal layer.

Abstract translation: 公开了一种集成电路（IC）基板，其包括形成在第一图案化金属层之间的第二图案化金属层。 形成在第一图案化金属层上的电介质层分离两个金属层。 在介电层和第二图案化金属层上形成非导电层。

公开(公告)号：WO2015171284A3

公开(公告)日：2015-12-30

申请号：PCT/US2015026199

申请日：2015-04-16

Applicant: QUALCOMM INC

Inventor： SONG YOUNG KYU ,  HWANG KYU-PYUNG ,  KIM DONG WOOK ,  ZHANG XIAONAN ,  LANE RYAN DAVID

IPC: H01G4/30 ,  H01G2/10 ,  H01G4/224 ,  H01G4/236 ,  H01G4/33 ,  H01G4/40 ,  H01L49/02 ,  H05K1/16 ,  H05K1/18

CPC classification number: H01G4/236 ,  H01G2/02 ,  H01G2/106 ,  H01G4/224 ,  H01G4/30 ,  H01G4/33 ,  H01G4/40 ,  H05K1/0231 ,  H05K1/115 ,  H05K1/182 ,  H05K1/185 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/10015 ,  Y10T29/42

Abstract: Some novel features pertain to package substrates that include a substrate having an embedded package substrate (EPS) capacitor with equivalent series resistance (ESR) control. The EPS capacitor includes two conductive electrodes separated by a dielectric or insulative thin film material and an equivalent series resistance (ESR) control structure located on top of each electrode connecting the electrodes to vias. The ESR control structure may include a metal layer, a dielectric layer, and a set of metal pillars which are embedded in the set of metal pillars are embedded in the dielectric layer and extend between the electrode and the metal layer. The EPS capacitor having the ESR control structure form an ESR configurable EPS capacitor which can be embedded in package substrates.

Abstract translation: 一些新颖的特征涉及包括具有嵌入式封装衬底（EPS）电容器和等效串联电阻（ESR）控制的衬底的封装衬底。 EPS电容器包括由介电或绝缘薄膜材料分开的两个导电电极以及位于将电极连接到通孔的每个电极的顶部上的等效串联电阻（ESR）控制结构。 ESR控制结构可以包括金属层，电介质层和嵌入在该组金属柱中的一组金属柱，该金属柱被嵌入在电介质层中并且在电极和金属层之间延伸。 具有ESR控制结构的EPS电容器形成ESR可配置EPS电容器，其可以嵌入封装基板中。