公开(公告)号：WO2017004316A3

公开(公告)日：2017-02-16

申请号：PCT/US2016040283

申请日：2016-06-30

Applicant: QUALCOMM INC

Inventor： GU SHIQUN ,  LI YUE ,  RADOJCIC RATIBOR

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L23/53228 ,  H01L28/75

Abstract: Copper (Cu) grain boundaries can move during a thermal cycle resulting in the Cu grain position being offset. Such Cu pumping can disturb the surface of a bottom metal, and can physically break a dielectric of a metal-insulator-metal (MIM) capacitor (410). By capping the bottom metal (420) under the MIM capacitor with an anchoring cap (425), Cu pumping is reduced or eliminated and the reliability of the MIM capacitor is improved.

Abstract translation: 铜（Cu）晶界可以在热循环期间移动，导致Cu晶粒位置偏移。 这种Cu泵送可以干扰底部金属的表面，并且可以物理地破坏金属 - 绝缘体 - 金属（MIM）电容器（410）的电介质。 通过使用固定帽（425）将MIM电容器下方的底部金属（420）加盖，减少或消除了Cu泵浦，提高了MIM电容器的可靠性。

公开(公告)号：SG11201900340QA

公开(公告)日：2019-03-28

申请号：SG11201900340Q

申请日：2017-07-25

Applicant: QUALCOMM INC

Inventor： KAKADE MANOJ ,  XU HAIYONG ,  ZANG RUEY KAE ,  LI YUE ,  ZHANG XIAONAN ,  HAU-RIEGE CHRISTINE

IPC: H01L21/60

Abstract: The present disclosure provides packages and methods for fabricating packages. A package may comprise a wafer-level package (WLP) layer comprising a WLP contact and a component within the WLP layer associated with a component depth. A conductive pillar is disposed on the WLP contact and comprises an opposite surface that forms an array pad. The package further comprises a mold over the WLP layer and at least partially surrounding the conductive pillar, wherein the mold compound and the array pad form a substantially planar land grid array (LGA) contact surface that is configured to couple the package to a land grid array. The LGA contact surface has a height that is equal to a selected LGA component height, and the selected LGA component height is equal to a difference between a keepout distance associated with a characteristic of the component within the WLP layer and the component depth.

公开(公告)号：AU2017316274A1

公开(公告)日：2019-01-31

申请号：AU2017316274

申请日：2017-07-25

Applicant: QUALCOMM INC

Inventor： KAKADE MANOJ ,  XU HAIYONG ,  ZANG RUEY KAE ,  LI YUE ,  ZHANG XIAONAN ,  HAU-RIEGE CHRISTINE

IPC: H01L21/60

Abstract: The present disclosure provides packages and methods for fabricating packages. A package (701) may comprise a wafer-level package (WLP) layer comprising first and second WLP contacts and first and second conductive pillars disposed on the first and second WLP contacts. Each conductive pillar comprises a surface opposite the WLP contact that forms an array pad (750-759). The array pads have different sizes. The package further comprises a mold (740) over the WLP layer and at least partially surrounding the conductive pillars, wherein the mold compound and the first array pads form a substantially planar LGA contact surface that is configured to couple the package to a land grid array.