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    METHOD FOR MANUFACTURING A STRUCTURE FOR FORMING A TRIDIMENSIONAL MONOLITHIC INTEGRATED CIRCUIT
    2.
    发明申请
    METHOD FOR MANUFACTURING A STRUCTURE FOR FORMING A TRIDIMENSIONAL MONOLITHIC INTEGRATED CIRCUIT 审中-公开
    制造用于形成三端单片集成电路的结构的方法

    公开(公告)号：WO2017167976A1

    公开(公告)日：2017-10-05

    申请号：PCT/EP2017/057717

    申请日：2017-03-31

    Applicant: SOITEC

    Inventor： FIGUET, Christophe ,  ECARNOT, Ludovic ,  NGUYEN, Bich-Yen ,  SCHWARZENBACH, Walter ,  DELPRAT, Daniel ,  RADU, Ionut

    IPC: H01L21/18 ,  H01L21/306 ,  H01L25/00

    Abstract: The invention relates to a method for manufacturing a structure comprising a first substrate (1) comprising at least one electronic component (10) likely to be damaged by a temperature higher than 400°C and a semi-conductor layer extending on said first substrate, characterised in that it comprises the following steps of: (a) providing a first bonding metal layer (11) on the first substrate (1), (b) providing a second substrate (2) comprising successively: -a semi-conductor base substrate (20), -a stack (21) of a plurality of semi-conductor epitaxial layers, a layer (210) of Si x Ge 1-x , with 0 ≤ x ≤1 being located at the surface of said stack (21) opposite to the base substrate (20),1-a second bonding metal layer (22), (c)bonding the first substrate and the second substrate through the first and second bonding metal layers(11, 22),said bonding step being carried out at a temperature lower than or equal to 400°C, (d) removing a part of the second substrate so as to transfer the layer (210) of Si x Ge 1-x on the first substrate(1), said removing comprising at least selectively chemically etching a layer of the second substrate (2) relative to the Si x Ge 1-x layer (210).

    Abstract translation: 本发明涉及一种用于制造结构的方法，所述结构包括第一基板（1）和第二基板（1），所述第一基板包括至少一个可能被高于400℃的温度损坏的电子部件（10） 其特征在于，它包括以下步骤：（a）在第一衬底（1）上提供第一键合金属层（11）;（b）提供第二衬底（2），该第二衬底（2）依次包括： ： - 半导体基础衬底（20）， - 多个半导体外延层的堆叠（21），Si x x Ge 1-x层（210） 其中0≤x≤1位于所述叠层（21）的与所述基底衬底（20）相对的表面处，1-第二接合金属层（22），（c）将所述第一衬底和 通过所述第一和第二键合金属层（11,22）连接所述第二衬底，所述键合步骤在低于或等于400℃的温度下进行，（d）除去部分所述s 第二衬底，以便在第一衬底（1）上转移Si x Ge 1-x的层（210），所述去除包括至少选择性地化学蚀刻层 （2）相对于Si 1 1 1-x 层（210）的第一衬底（2）。

    HETEROSTRUCTURE AND METHOD OF FABRICATION
    3.
    发明申请
    HETEROSTRUCTURE AND METHOD OF FABRICATION 审中-公开
    外部结构和制造方法

    公开(公告)号：WO2016198542A1

    公开(公告)日：2016-12-15

    申请号：PCT/EP2016/063198

    申请日：2016-06-09

    Applicant: SOITEC

    Inventor： CASTEX, Arnaud ,  DELPRAT, Daniel ,  ASPAR, Bernard ,  RADU, Ionut

    IPC: H01L41/08 ,  H01L41/312

    CPC classification number: H03H9/02834 ,  H01L41/0805 ,  H01L41/312 ,  H01L41/313 ,  H01L41/332 ,  H01L41/337 ,  H03H3/10 ,  H03H9/02574 ,  H03H9/6496

    Abstract: The present invention relates to a heterostructure, in particular a piezoelectric structure, comprising a cover layer, in particular a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

    Abstract translation: 本发明涉及异质结构，特别是压电结构，其包括覆盖层，特别是压电材料层，覆盖层的材料具有第一热膨胀系数，组装到支撑衬底，支撑衬底 具有与第一热膨胀系数几乎不同的第二热膨胀系数，其中覆盖层至少包括从界面延伸到覆盖层中的凹部及其制造方法。

    PROCEDE DE REPORT D'UNE COUCHE MINCE SUR UN SUBSTRAT SUPPORT MUNI D'UNE COUCHE DE PIEGEAGE DE CHARGES
    6.
    发明申请
    PROCEDE DE REPORT D'UNE COUCHE MINCE SUR UN SUBSTRAT SUPPORT MUNI D'UNE COUCHE DE PIEGEAGE DE CHARGES 审中-公开

    公开(公告)号：WO2022023630A1

    公开(公告)日：2022-02-03

    申请号：PCT/FR2021/051140

    申请日：2021-06-23

    Applicant: SOITEC

    Inventor： CLEMENCEAU, Bruno ,  ECARNOT, Ludovic ,  GHORBEL, Aymen ,  BROEKAART, Marcel ,  DELPRAT, Daniel ,  ROUCHIER, Séverin ,  THIEFFRY, Stéphane ,  DURET, Carine

    IPC: H01L21/762 ,  H01L21/02 ,  H01L21/3105

    Abstract: L'invention porte sur un procédé de report d'une couche mince (5) sur un substrat support (1) comprenant la préparation d'un substrat support (1) à l'aide d'un procédé de préparation comprenant la fourniture d'un substrat de base (3) présentant, sur une face principale, une couche de piégeage de charges (2) et la formation d'une couche diélectrique (4) présentant une épaisseur supérieure à 200nm sur la couche de piégeage de charges (2). La formation de la couche diélectrique (4) met simultanément en œuvre le dépôt et la pulvérisation ionique de la couche diélectrique. Le procédé de report comprend également l'assemblage, par adhésion moléculaire et sans préparer la face libre de la couche diélectrique (4) par polissage, d'un substrat donneur à la couche diélectrique (4) du substrat support (1), le substrat donneur présentant un plan de fragilisation définissant la couche mince (5). Le procédé comprend enfin la fracture du substrat donneur au niveau du plan de fragilisation pour libérer la couche mince (5) et la reporter sur le substrat support (1).

    METHOD FOR MANUFACTURING A SEMICONDUCTOR ON INSULATOR TYPE STRUCTURE BY LAYER TRANSFER
    7.
    发明申请
    METHOD FOR MANUFACTURING A SEMICONDUCTOR ON INSULATOR TYPE STRUCTURE BY LAYER TRANSFER 审中-公开

    公开(公告)号：WO2019155081A1

    公开(公告)日：2019-08-15

    申请号：PCT/EP2019/053427

    申请日：2019-02-12

    Applicant: SOITEC

    Inventor： DELPRAT, Daniel ,  PARISSI, Damien ,  BROEKAART, Marcel

    IPC: H01L21/762

    Abstract: The invention relates to a method for manufacturing a semiconductor on insulator type structure by transfer of a layer from a donor substrate onto a receiver substrate, comprising the following steps: a) the supply of the donor substrate and the receiver substrate, b) the formation in the donor substrate of an embrittlement zone delimiting the layer to transfer, c) the bonding of the donor substrate on the receiver substrate, the surface of the donor substrate opposite to the embrittlement zone with respect to the layer to transfer being at the bonding interface, d) the detachment of the donor substrate along the embrittlement zone enabling the transfer of the layer to transfer onto the receiver substrate, the transfer method being characterised in that it comprises, before the bonding step, a step of controlled modification of the curvature of the donor substrate and/or the receiver substrate so as to move the substrates away from each other at least in one region of their periphery, the face or the two faces intended to form the bonding interface of the donor substrate and/or the receiver substrate being deformed so as to have a curvature amplitude (Bw) greater than or equal to 136 μm.

    SUBSTRATE AND METHOD FOR PRODUCING A SUBSTRATE
    8.
    发明申请
    SUBSTRATE AND METHOD FOR PRODUCING A SUBSTRATE 审中-公开
    用于生产基材的基板和方法

    公开(公告)号：WO2016062674A1

    公开(公告)日：2016-04-28

    申请号：PCT/EP2015/074181

    申请日：2015-10-19

    Applicant: SOITEC

    Inventor： RADU, Ionut ,  KONONCHUK, Oleg ,  MAZURE, Carlos ,  DELPRAT, Daniel

    IPC: H01L21/762

    CPC classification number: H01L21/76254

    Abstract: A substrate (1) for producing transistors having fully depleted channels, with the substrate comprising the following stacking: - a support (6) comprising contaminant species liable to diffuse; - a barrier layer for encapsulating (5) the support and able to prevent the diffusion of the contaminant species; - an intermediate layer (4) made of a polycrystalline or amorphous semiconductor material on the encapsulation barrier layer (5); - an electrically insulating layer (3) having a thickness ranging from 2 to 50 nanometers on the intermediate layer ( 4 ); - a semiconductive upper layer (2) having a thickness ranging from 2 to 50 nanometers on the electrically insulating layer (3) and free of contaminant species.

    Abstract translation: 一种用于制造具有完全耗尽通道的晶体管的衬底（1），其中衬底包括以下堆叠： - 包含易于扩散的污染物质的支撑体（6） - 阻挡层，用于封装（5）载体并能够防止污染物质的扩散; - 在所述封装阻挡层（5）上由多晶或非晶半导体材料制成的中间层（4）; - 在中间层（4）上具有2至50纳米厚度的电绝缘层（3）; - 在电绝缘层（3）上具有2至50纳米厚度且不含污染物质的半导体上层（2）。

    METHOD FOR TRANSFERRING A LAYER OF SEMICONDUCTOR, AND SUBSTRATE COMPRISING A CONFINEMENT STRUCTURE
    9.
    发明申请
    METHOD FOR TRANSFERRING A LAYER OF SEMICONDUCTOR, AND SUBSTRATE COMPRISING A CONFINEMENT STRUCTURE 审中-公开
    用于传输半导体层的方法和包含约束结构的衬底

    公开(公告)号：WO2012175561A1

    公开(公告)日：2012-12-27

    申请号：PCT/EP2012/061848

    申请日：2012-06-20

    Applicant: SOITEC ,  LALLEMENT, Fabrice ,  FIGUET, Christophe ,  DELPRAT, Daniel

    Inventor： LALLEMENT, Fabrice ,  FIGUET, Christophe ,  DELPRAT, Daniel

    IPC: H01L21/762

    CPC classification number: H01L21/76254 ,  H01L29/267

    Abstract: The invention relates to a method for transferring a layer of semiconductor, characterized in that it comprises the steps consisting in: -providing (E1) a donor substrate (3) comprising a useful layer (2) consisting of a semiconductor material, and a confinement structure (5), comprising a confinement layer (4), consisting of a semiconductor material, the confinement layer (4)with a chemical composition different than the useful layer (2), and two protective layers (6, 7)of semiconductor material, and with a chemical composition distinct from the confinement layer (4), the protective layers being arranged on both sides of the confinement layer (4), -introducing (E3) ions (15) int he donor substrate (3), -bonding ( E4) the donor substrate (3)and a receiver substrate (10), -subjecting (E5) the donor substrate (3) and the receiver substrate (10) to heat treatment comprising an increase in temperature, during which the confinement layer (4) attracts the ions (15) in order to concentrate them in said confinement layer (4), and -detaching (S6) the donor substrate (3) from the receiver substrate (10) by breaking at said confinement layer (4).

    Abstract translation: 本发明涉及一种用于转移半导体层的方法，其特征在于其包括以下步骤：提供（E1）施主衬底（3），其包括由半导体材料构成的有用层（2）和限制 结构（5），包括：由半导体材料构成的约束层（4），具有不同于有用层（2）的化学组成的约束层（4），以及α两个保护层（6,7） 半导体材料，并且具有与限制层（4）不同的化学组成，保护层布置在限制层（4）的两侧，在供体衬底（3）上引入（E3）离子（15）， （E4）施主衬底（3）和接收器衬底（10）， - 施主（E5）施主衬底（3）和接受器衬底（10）以进行包括温度升高的热处理，在此期间限制 层（4）吸引离子（15）以便集中 它们在所述限制层（4）中，并且通过在所述限制层（4）处断开，从所述接收器基板（10） - 提取（S6）所述施主衬底（3）。

    QUANTUM WELL THERMOELECTRIC COMPONENT FOR USE IN A THERMOELECTRIC DEVICE
    10.
    发明申请
    QUANTUM WELL THERMOELECTRIC COMPONENT FOR USE IN A THERMOELECTRIC DEVICE 审中-公开
    用于热电装置的量子阱热电组件

    公开(公告)号：WO2012140483A1

    公开(公告)日：2012-10-18

    申请号：PCT/IB2012/000689

    申请日：2012-04-04

    Applicant: SOITEC ,  DELPRAT, Daniel ,  FIGUET, Christophe ,  KONONCHUK, Oleg

    Inventor： DELPRAT, Daniel ,  FIGUET, Christophe ,  KONONCHUK, Oleg

    IPC: H01L35/26 ,  H01L21/02 ,  H01L35/22

    CPC classification number: H01L35/02 ,  H01L35/22 ,  H01L35/26 ,  H01L35/34

    Abstract: A quantum well thermoelectric component for use in a thermoelectric device based on the thermoelectric effect, • comprising a stack (1 ) of layers (3, 4) of two materials respectively made on the basis of silicon and silicon-germanium, • the first of said two materials, made on the basis of silicon, defining a barrier semiconductor material and • the second of said two materials, made on the basis of silicon-germanium, defining a conducting semiconductor material, • said barrier semiconductor material having a band gap higher than the band gap of said conducting semiconductor material, wherein • the conducting semiconductor material is an alloy comprising silicon, germanium and at least a lattice matching element, said lattice matching element(s) being present in order to control a lattice parameter mismatch between the barrier layer (3) made of the barrier semiconductor material and the conducting layer (4) made of the conducting semiconductor material.

    Abstract translation: 一种用于基于热电效应的热电装置的量子阱热电组件，包括分别基于硅和硅 - 锗制成的两种材料的层（3,4）的叠层（1），第一层 所述两种材料是在硅基的基础上制成的，限定了一种阻挡半导体材料，并且所述两种材料中的第二种是基于硅 - 锗制成的，限定了导电半导体材料，所述阻挡半导体材料具有较高的带隙 所述导电半导体材料是包含硅，锗和至少晶格匹配元素的合金，所述晶格匹配元件存在以控制所述导电半导体材料的晶格参数失配， 由阻挡半导体材料制成的阻挡层（3）和由导电半导体材料制成的导电层（4）。

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