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    METHODS OF FORMING SEMICONDUCTOR STRUCTURES INCLUDING MEMS DEVICES AND INTEGRATED CIRCUITS ON OPPOSING SIDES OF SUBSTRATES, AND RELATED STRUCTURES AND DEVICES
    1.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR STRUCTURES INCLUDING MEMS DEVICES AND INTEGRATED CIRCUITS ON OPPOSING SIDES OF SUBSTRATES, AND RELATED STRUCTURES AND DEVICES 审中-公开
    形成包括MEMS器件的半导体结构的方法和基板对准面的集成电路及其相关结构和器件

    公开(公告)号：WO2014020387A1

    公开(公告)日：2014-02-06

    申请号：PCT/IB2013/001487

    申请日：2013-07-08

    Applicant: SOITEC

    Inventor： SADAKA, Mariam ,  ASPAR, Bernard ,  LAGAHE BLANCHARD, Chrystelle

    IPC: B81C1/00

    CPC classification number: B81B7/007 ,  B81B2201/0271 ,  B81B2207/012 ,  B81B2207/015 ,  B81C1/00238 ,  B81C1/00246 ,  B81C1/00301 ,  B81C2203/0735 ,  B81C2203/0792 ,  H01L2224/16 ,  H03H9/10

    Abstract: Methods of forming semiconductor devices comprising integrated circuits and microelectromechanical system (MEMS) devices operatively coupled with the integrated circuits involve the formation of an electrically conductive via extending at least partially through a substrate from a first major surface of the substrate toward an opposing second major surface of the substrate, and the fabrication of at least a portion of an integrated circuit on the first major surface of the substrate. A M EMS device is provided on the second major surface of the substrate, and the MEMS device is operatively coupled with the integrated circuit using the at least one electrically conductive via. Structures and devices are fabricated using such methods.

    Abstract translation: 形成包括集成电路的半导体器件和与集成电路可操作耦合的微机电系统（MEMS）器件的方法包括形成导电通孔，该导电通孔至少部分地穿过衬底，从衬底的第一主表面向相对的第二主表面延伸 的衬底，以及在衬底的第一主表面上制造集成电路的至少一部分。 在衬底的第二主表面上提供M EMS器件，并且MEMS器件使用至少一个导电通孔与集成电路操作耦合。 使用这种方法制造结构和装置。

    STRUCTURE POUR APPLICATION RADIOFRÉQUENCE
    2.
    发明申请
    STRUCTURE POUR APPLICATION RADIOFRÉQUENCE 审中-公开

    公开(公告)号：WO2018142052A1

    公开(公告)日：2018-08-09

    申请号：PCT/FR2018/050196

    申请日：2018-01-29

    Applicant: SOITEC

    Inventor： DESBONNETS, Eric ,  ASPAR, Bernard

    IPC: H01L21/762 ,  H01L29/786

    Abstract: L'invention concerne une structure (100) pour application radiofréquence comprenant : Un substrat support (1) à haute résistivité dont une face avant (1a) définit un plan principal, Une couche de piégeage de charges (2) disposée sur la face avant (1a) du substrat support (1), Une première couche diélectrique (3) disposée sur la couche de piégeage (2), Une couche active (4) disposée sur la première couche diélectrique (3), La structure (100) étant remarquable en ce qu'elle comprend au moins une électrode enterrée (10) disposée au dessus ou dans la couche de piégeage (2), l'électrode (10) comprenant une couche conductrice (11) et une deuxième couche diélectrique (13).

    METHODS FOR FABRICATION OF SEMICONDUCTOR STRUCTURES USING LASER LIFT-OFF PROCESS, AND RELATED SEMICONDUCTOR STRUCTURES
    3.
    发明申请
    METHODS FOR FABRICATION OF SEMICONDUCTOR STRUCTURES USING LASER LIFT-OFF PROCESS, AND RELATED SEMICONDUCTOR STRUCTURES 审中-公开
    使用激光提升过程制造半导体结构的方法和相关半导体结构

    公开(公告)号：WO2014020390A1

    公开(公告)日：2014-02-06

    申请号：PCT/IB2013/001490

    申请日：2013-07-08

    Applicant: SOITEC

    Inventor： SADAKA, Mariam ,  ASPAR, Bernard ,  LAGAHE BLANCHARD, Chrystelle

    IPC: H01L21/78 ,  H01L33/00

    CPC classification number: H01L21/78 ,  H01L21/268 ,  H01L21/304 ,  H01L21/6835 ,  H01L21/7813 ,  H01L33/0079

    Abstract: Methods of fabricating a semiconductor structure include bonding a carrier wafer over a substrate, removing at least a portion of the substrate, transmitting laser radiation through the carrier wafer and weakening a bond between the substrate and the carrier wafer, and separating the carrier wafer from the substrate. Other methods include forming circuits over a substrate, forming trenches in the substrate to define unsingulated semiconductor dies, bonding a carrier substrate over the unsingulated semiconductor dies, transmitting laser radiation through the carrier substrate and weakening a bond between the unsingulated semiconductor dies and the carrier substrate, and separating the carrier substrate from the unsingulated semiconductor dies. Some methods include thinning at least a portion of the substrate, leaving the plurality of unsingulated semiconductor dies bonded to the carrier substrate.

    Abstract translation: 制造半导体结构的方法包括将载体晶片结合在衬底上，去除衬底的至少一部分，通过载体晶片传输激光辐射并削弱衬底和载体晶片之间的结合，并将载体晶片与 基质。 其他方法包括在衬底上形成电路，在衬底中形成沟槽以限定未加掩模的半导体管芯，将载体衬底粘合在未加掩模的半导体管芯上方，将激光辐射传输通过载体衬底并削弱未加掩模的半导体管芯与载体衬底之间的接合 并且将载体衬底与未折叠的半导体管芯分离。 一些方法包括使衬底的至少一部分变薄，使得多个未折叠半导体管芯接合到载体衬底。

    HETEROSTRUCTURE AND METHOD OF FABRICATION
    4.
    发明申请
    HETEROSTRUCTURE AND METHOD OF FABRICATION 审中-公开
    外部结构和制造方法

    公开(公告)号：WO2016198542A1

    公开(公告)日：2016-12-15

    申请号：PCT/EP2016/063198

    申请日：2016-06-09

    Applicant: SOITEC

    Inventor： CASTEX, Arnaud ,  DELPRAT, Daniel ,  ASPAR, Bernard ,  RADU, Ionut

    IPC: H01L41/08 ,  H01L41/312

    CPC classification number: H03H9/02834 ,  H01L41/0805 ,  H01L41/312 ,  H01L41/313 ,  H01L41/332 ,  H01L41/337 ,  H03H3/10 ,  H03H9/02574 ,  H03H9/6496

    Abstract: The present invention relates to a heterostructure, in particular a piezoelectric structure, comprising a cover layer, in particular a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

    Abstract translation: 本发明涉及异质结构，特别是压电结构，其包括覆盖层，特别是压电材料层，覆盖层的材料具有第一热膨胀系数，组装到支撑衬底，支撑衬底 具有与第一热膨胀系数几乎不同的第二热膨胀系数，其中覆盖层至少包括从界面延伸到覆盖层中的凹部及其制造方法。

    METHODS OF FORMING SEMICONDUCTOR STRUCTURES INCLUDING A CONDUCTIVE INTERCONNECTION, AND RELATED STRUCTURES
    5.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR STRUCTURES INCLUDING A CONDUCTIVE INTERCONNECTION, AND RELATED STRUCTURES 审中-公开
    形成导电互连的半导体结构的方法及相关结构

    公开(公告)号：WO2014020389A1

    公开(公告)日：2014-02-06

    申请号：PCT/IB2013/001489

    申请日：2013-07-08

    Applicant: SOITEC

    Inventor： SADAKA, Mariam ,  ASPAR, Bernard ,  LAGAHE BLANCHARD, Chrystelle

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81B7/0006 ,  B81B2207/012 ,  B81B2207/096 ,  B81C1/00238

    Abstract: Methods are used to form semiconductor structures and microelectromechanical system (MEMS) devices that include an electrical interconnection. One or more trenches are formed in a doped semiconductor substrate to form at least one doped semiconductor element defined by the one or more trenches, a substrate is attached to the doped semiconductor substrate and to the at least one doped semiconductor element, and material is removed from the doped semiconductor substrate to expose the one or more trenches and to isolate the at least one doped semiconductor element from adjacent portions of the doped semiconductor substrate. Semiconductor structures and MEMS devices including an electrical interconnection are formed by such methods. Semiconductor structures and MEMS devices include transducers formed from a doped semiconductor material.

    Abstract translation: 方法用于形成包括电互连的半导体结构和微机电系统（MEMS）装置。 在掺杂半导体衬底中形成一个或多个沟槽，以形成由一个或多个沟槽限定的至少一个掺杂半导体元件，衬底附接到掺杂半导体衬底和至少一个掺杂半导体元件，并且去除材料 从所述掺杂半导体衬底暴露所述一个或多个沟槽并且将所述至少一个掺杂半导体元件与所述掺杂半导体衬底的相邻部分隔离。 通过这种方法形成包括电互连的半导体结构和MEMS器件。 半导体结构和MEMS器件包括由掺杂半导体材料形成的换能器。

    PROCEDE DE TRANSFERT DE PLAQUES
    9.
    发明授权
    PROCEDE DE TRANSFERT DE PLAQUES 有权
    程序用于转移板

    公开(公告)号：EP1759411B1

    公开(公告)日：2012-05-30

    申请号：EP05776391.4

    申请日：2005-06-02

    Applicant: Soitec

    Inventor： ASPAR, Bernard ,  LAGAHE-BLANCHARD, Chrystelle

    IPC: H01L21/683

    CPC classification number: H01L21/6835 ,  H01L2221/68359 ,  H01L2221/68368

    Abstract: The invention relates to a method for preparing a thin layer (28) or a chip to be transferred to another substrate. According to said method, at least one layer, a so-called adhesion layer (25), and at least one other layer, a so-called first boundary layer (22), is formed above the surface of the thin layer or the chip, the adhesion layer consisting of a material which is etched in a selective manner in relation to the material of the boundary layer.

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