公开(公告)号：JP2005026705A

公开(公告)日：2005-01-27

申请号：JP2004247636

申请日：2004-08-27

Applicant: Sony Corp ,  ソニー株式会社

Inventor： KANETANI YASUHIRO ,  YAMAZAKI MASARU ,  FUJINO MASAHIRO ,  SUZUKI NOBUAKI ,  KANETANI MIDORI

IPC: G02F1/1368 ,  H01L21/20 ,  H01L21/336 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To form a uniform polycrystalline semiconductor thin film through laser annealing. SOLUTION: A substrate 5 having an insulating layer whose thermal conductivity is comparatively low, and whose thickness is 20nm or larger, is prepared. Next, an amorphous silicon thin film 6 whose thermal conductivity is comparatively high and whose thickness is 35nm or smaller, is formed on the insulating layer. After this, the amorphous silicon thin film 6 is shot-irradiated successively with a laser beam 2 which is moved and scanned, to be applied with thermal energy, and it is converted into the polycrystalline silicon thin film, so that the laser beam of previous shots and the laser beam of the following shots partially overlap in a section with each other. The polycrystalline silicon can grow in a uniform particle size, by setting the thickness of the amorphous silicon thin film 6 to 35nm or smaller. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：通过激光退火形成均匀的多晶半导体薄膜。 解决方案：制备具有导热率相对较低，厚度为20nm以上的绝缘层的基板5。 接着，在绝缘层上形成热导率比较高，厚度为35nm以下的非晶硅薄膜6。 之后，用移动扫描的激光束2依次对无定形硅薄膜6进行喷射照射，施加热能，并将其转换为多晶硅薄膜，使得先前的 以下拍摄的照片和激光束在一部分彼此部分重叠。 通过将非晶硅薄膜6的厚度设定为35nm以下，可以使均匀的粒径生长多晶硅。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JPH08279618A

公开(公告)日：1996-10-22

申请号：JP10474795

申请日：1995-04-04

Applicant: SONY CORP

Inventor： FUJINO MASAHIRO

IPC: H01L29/786 ,  H01L21/336

Abstract: PURPOSE: To markedly lessen a rear-side exposure time in a thin film semiconductor device manufacturing process and to restrain a thin film semiconductor device from dispersing in parasitic capacitance by a method wherein a thin polycrystalline silicon film is used as an active layer, and a thin bottom-gate type film transistor is formed through a rear-side exposure process. CONSTITUTION: A light shading gate electrode 2 is formed on the surface of a transparent substrate 1, a gate insulating film 3 is formed thereon, and furthermore a thin polycrystalline silicon film 4 is formed on the gate insulating film 3. Then, an insulating film 5 is formed on the thin polycrystalline silicon film 4, a photoresist film is formed thereon, and a photoresist pattern 6 is formed conforming to the gate electrode 2. Then, the photoresist pattern 6 is worked into a channel stopper 7 conforming to the gate electrode 2. Lastly, the thin polycrystaline silicon film 4 is dopes with impurities using the channel stopper 7 as a mask to provide a source region S and a drain region D. By this setup, a thin bottom-gate film transistor can be formed integrated.

公开(公告)号：JP2003115594A

公开(公告)日：2003-04-18

申请号：JP2001310560

申请日：2001-10-05

Applicant: SONY CORP ,  ST LCD KK

Inventor： TANAKA TSUTOMU ,  MANO MICHIO ,  TORIYAMA SHIGETAKA ,  FUJINO MASAHIRO ,  KOMATSU HIROSHI ,  TAKEDA HIROHISA

IPC: G02F1/1368 ,  H01L21/302 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To improve the yield of a product by preventing defects in gate breakdown strength in a bottom gate type TFT. SOLUTION: The manufacturing method of a bottom gate type TFT 100A includes a step (1) of forming a gate electrode on a substrate, a step (2) of forming a gate insulating film on the gate electrode 2, a step (3) of forming a laminate made up of an protective insulating film 8 having a film thickness of 100 nm or smaller while an active-layer antecedent film (polysilicon film 7) and the protective insulating film 8 are laminated on the gate insulating film, a step (4) of implanting a dopant in an LDD region or in a source/drain region of the active-layer precursor film 8 through the protective insulating film 8, a step (5) of activating the implanted dopant and causing the other non-dopant part to be an active layer, a step (6) of modifying the quality of all or part of the protective insulating film 8, a step (7) of forming an interlayer insulating film on the modified protective insulating film 8, and a step (8) of forming a source/drain electrode on the interlayer insulating film.

公开(公告)号：JP2002162646A

公开(公告)日：2002-06-07

申请号：JP2000361080

申请日：2000-11-28

Applicant: SONY CORP

Inventor： FUJINO MASAHIRO

IPC: G02F1/133 ,  G02F1/1335 ,  G02F1/1343 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/30 ,  H01L21/336 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To simplify the manufacturing process of an active matrix reflection type liquid crystal display device to enhance productivity. SOLUTION: In a method for manufacturing the active matrix reflection type liquid crystal display device, a stage A for forming an interlayer insulating film 5 on a silicon film 3 on which a source S and a drain D of a TFT are formed, a stage B for forming a photoresist layer 6 on the interlayer insulating film 5, a stage C for patterning the photoresist layer 6 in a specific pattern using a mask having a pattern of resolution limit or below formed in a part corresponding to a reflection electrode 10 to be formed as a photo mask 20 of the photoresist layer 6 and a stage D for etching the interlayer insulating film 5 using the photoresist layer 6 patterned in the stage C as an etching mask are performed as the stages for forming and processing the interlayer insulating film. After the stage D, a source electrode S1, a signal wiring, a drain electrode D1 and a reflection electrode 10 are simultaneously formed by depositing a metal film 11.

公开(公告)号：JPH11194335A

公开(公告)日：1999-07-21

申请号：JP36921497

申请日：1997-12-30

Applicant: SONY CORP

Inventor： NAKAMURA SHINJI ,  FUJINO MASAHIRO ,  SATO MAKI

IPC: G02F1/1335 ,  G02F1/136 ,  G02F1/1368

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method by which misalignment between a driving substrate and an opposed substrate can be reduced by forming a color filter on the driving substrate and also the color filter forming process can be simplified. SOLUTION: A thin film transistor 22 is formed on a glass substrate 21 of a driving substrate side, and then, a photosensitive resin film 23A is formed. After the photosensitive resin 23A has been dried by heating, a relative alignment is carried out between a coloring solution jet nozzle 7 and the driving substrate 2, and red coloring solution 7a, green coloring solution 7b, and blue coloring solution 7c are jetted simultaneously from the coloring solution jet nozzle 7 onto each picture element column on the photosensitive resin film 23A, which is heated further. Thus, a color filter layer 23 including the red filter, the green filter, and the blue filter is formed.

公开(公告)号：JPH0945930A

公开(公告)日：1997-02-14

申请号：JP21271695

申请日：1995-07-28

Applicant: SONY CORP

Inventor： HAYASHI HISAO ,  FUJINO MASAHIRO ,  YAMAZAKI MASARU

IPC: H01L21/336 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To ensure sufficient on-current of a thin film transistor while suppressing the off-current. SOLUTION: A thin film transistor is provided with a laminated structure formed by laminating a semiconductor thin film 1, a gate electrode 2 provided with a prescribed pattern and a gate insulating film 3 between the film 1 and the electrode 2. The semiconductor thin film 1 is provided with a channel area 4, a high concentration impurity area 5 and a low concentration impurity area 6. The semiconductor thin film 1 is provided with an internal part IN included in the pattern of the gate electrode 2 and an external part OUT positioned outside the pattern. The channel area 4 is formed on the internal part IN, and the high concentration impurity area 5 is formed on the external part OUT. The low concentration impurity area 6 is positioned between the channel area 4 and the high concentration impurity area 5, and at least a part of the area 6 is included in the internal part IN. The on current is prevented from reducing by modulating the low concentration impurity area 6 by gate potential.

公开(公告)号：JPH0933953A

公开(公告)日：1997-02-07

申请号：JP20658495

申请日：1995-07-19

Applicant: SONY CORP

Inventor： FUJINO MASAHIRO ,  KUKI MIDORI

IPC: G02F1/136 ,  G02F1/1368 ,  G09F9/30 ,  H01L21/336 ,  H01L21/822 ,  H01L27/04 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To prevent the variance and dielectric strength deterioration of an auxiliary capacitor integrated and formed at the same time with a bottom gate type thin film transistor(TFT). SOLUTION: A pixel electrode 1, the TFT 2 which supplies signal charges to the pixel electrode 1, and the auxiliary capacitor 3 which hold the supplied signal charges subsidiarily are integrated and formed on an insulating substrate 4. The TFT 2 has bottom gate type structure equipped with a gate electrode 5 patterned and formed on the insulating substrate 4, a gate insulating film 6 formed thereupon, a semiconductor thin film 7 formed thereupon to constitute a channel part Ch, and a drain electrode 8 and a source electrode 9 which are connected to the channel part Ch. The auxiliary capacitor 3 has laminate structure obtained by stacking a lower electrode 12 in the same layer with the gate electrode 5, a dielectric film 13 in the same layer with the gate insulating film 6, and an upper electrode 15 in order. This upper electrode 14 is interposed between the pixel electrode 1 and drain electrode 8 which are separated from each other to electrically connect them to each other and also constituted in the same layer with the semiconductor thin film 7.

公开(公告)号：JPH0818056A

公开(公告)日：1996-01-19

申请号：JP14503294

申请日：1994-06-27

Applicant: SONY CORP

Inventor： FUJINO MASAHIRO

IPC: H01L21/265 ,  H01L21/266 ,  H01L21/336 ,  H01L29/78 ,  H01L29/786

Abstract: PURPOSE:To reduce the ion implantation process, and lessen the manhour in manufacture, and enlarge the freedom in design, and further, improve the accuracy in alignment between a source and a drain region and an offset region. CONSTITUTION:This is the manufacture of a field effect transistor which has a process of forming an ion implantation stopping layer 25 on a semiconductor layer 22, a process of processing this ion implantation stopping layer 25 with patterns including a channel region and an offset region 24, and processing the end on drain side at least of the ion implantation stopping layer 25, and a process of forming source and drain regions 23 having offset regions 24 on the semiconductor layer 22 by implanting ions of impurities from above this ion implantation stopping layer 25.

公开(公告)号：JPS62195832A

公开(公告)日：1987-08-28

申请号：JP3696386

申请日：1986-02-21

Applicant: SONY CORP

Inventor： FUJINO MASAHIRO

IPC: H01J1/78 ,  H01J1/34 ,  H01J29/45

Abstract: PURPOSE:To stabilize the heat-resisting property, and saturating property, and the like, and improve the seizure performance, by furnishing a high density plain portion and gradually lower density sloped portions connecting thereto in the As density distribution composing a layer at the electron gun side, neighboring to a sensitizer layer. CONSTITUTION:At the rear side of a photoconductive membrane 3b of the second layer, a P-type photoconductive membrane 3c' of the third layer shown as C area is spread in about 250Angstrom thick in the thickness direction. The front half membrane of the third layer photoconductive membrane 3c' with about 50Angstrom thick has the density distribution of Se 75wt% and As 25wt%, for example, and at the rear half membrane with 200Angstrom thick, the density distribution is converted with Se 75-95wt%, and As 25-5wt%, for example. And at the rear side of the photoconductive membrane 3c', a P-type photoconductive membrane 3d' shown as D area is spread evenly on all the surface, with Se 95wt% and As 5wt%, for example. Therefore, even though little amount of As is used, the heat-resisting and the saturating properties and the like can be stabilized, and a seizure performance can be improved.

公开(公告)号：JP2001291870A

公开(公告)日：2001-10-19

申请号：JP2000105304

申请日：2000-04-06

Applicant: SONY CORP

Inventor： TANAKA TSUTOMU ,  FUJINO MASAHIRO ,  HAYASHI HISAO

IPC: G02F1/136 ,  G02F1/1368 ,  G09F9/00 ,  G09F9/30 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L27/13 ,  H01L27/32 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To improve productivity by reducing manufacturing processes, to prevent the defect in breakdown voltage of a gate insulating film, and to improve the yield of a product in a bottom gate type TFT. SOLUTION: This bottom gate type TFT 100A is manufactured by a process (1) for forming a gate electrode 2 on a substrate 1, a process (2) for forming a gate insulating film 6 on the gate electrode 2, a process (3) for forming a laminated body in which an active layer precursor film (polysiliocn film 7) and a protecting insulating film 8 are laminated on the gate insulting film 6 so that the protecting insulating film 8 can have thickness of 100 nm or less, a process (4) for injecting dopant through the protecting insulating film 8 into an LDD area 9 or a source drain area 10 of the active layer precursor film, and a process (5) for activating the implanted dopant and for forming the dopand non-implanted part as an active layer. Also, a liquid crystal display device 200A or an organic EL device 300 are manufactured by using the TFT 100A.