公开(公告)号：JP2000216087A

公开(公告)日：2000-08-04

申请号：JP1249899

申请日：1999-01-20

Applicant: SONY CORP

Inventor： INO MASUMITSU ,  URAZONO TAKENOBU ,  TAKATOKU MASATO ,  SUGANO YUKIYASU ,  FUJINO MASAHIRO ,  MANO MICHIO ,  ASANO AKIHIKO

IPC: H01L21/20 ,  G02F1/136 ,  G02F1/1365 ,  G02F1/1368 ,  H01L21/268 ,  H01L21/336 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To obtain a high-quality polycrystalline thin film by improving a semiconductor thin film crystallizing method using a laser beam. SOLUTION: The semiconductor thin film manufacturing method comprises an anneal step of irradiating a laser beam to convert a semiconductor thin film 4 to a polycrystal after a step of forming the non-single crystal semiconductor thin film 4 on the surface of a substrate 0. In the anneal step a laser beam pulse having an emission time width of 50 ns or more from the rise to fall and a fixed sectional area is at least once irradiated to convert the semiconductor film 4 contained in an irradiating region corresponding to its sectional area en bloc to the polycrystal wherein the energy intensity of the laser beam from the rise to fall is controlled to give desired variations. This enables the polycrystal to be of a large size or to be uniformized. For irradiating the laser beam, the substrate 0 may be disposed in a non-oxidative atmosphere and heated or cooled.

公开(公告)号：JPH0955440A

公开(公告)日：1997-02-25

申请号：JP20979695

申请日：1995-08-17

Applicant: SONY CORP

Inventor： MANO MICHIO

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/8244 ,  H01L23/485 ,  H01L23/522 ,  H01L27/11

Abstract: PROBLEM TO BE SOLVED: To simplify the manufacturing steps of semiconductor device by connecting a metallic wiring layer to a substrate by a tungsten buried electrode and by composing local wiring connecting holes for connecting the holes approximate to each other also of the tungsten barrier electrode. SOLUTION: Trench isolation T1 is used as for the element isolation technology in the case of a complete CMOS type SRAM. In such a structure, the diffused layer of a transistor Tr3 is connected to an aluminum wiring layer 1Al by tungsten blankets BL1, BL2 through the intermediary of adherent layer Ad covering respective inner surfaces of the first connecting hole CVSS 1 and the second connecting hole CVSS 2 connecting to the former. Besides, interconnects L1, L2, composed of the adherent layer Ad1 are connected to gate electrodes connected to G1, G2 respectively by shared contacts C1, C2. Furthermore, tungsten buried electrode BL1 is buried in respective connecting holes CVSS 1 and C1-C4.

公开(公告)号：JPH08186179A

公开(公告)日：1996-07-16

申请号：JP33834094

申请日：1994-12-28

Applicant: SONY CORP

Inventor： MANO MICHIO

IPC: H01L27/092 ,  H01L21/8238

Abstract: PURPOSE: To enable an well balanced design in terms of design rule by balancing the characteristics between both transistors by forming the conductor type of the each gate electrode of a P channel transistor and an N channel transistor to be a P-type. CONSTITUTION: After forming SiO2 film 12 on the surface of a Si substrate 11, an N well 14 and a P well 31 are formed on each forming region of a PMOS transistor 26 and an NMOS transistor 27. An As ion is injected into both of the N well 14 and the P well 31, and an N-region 32 for adjusting threshold voltage is formed. An SiO2 film 15 is formed on an Si substrate 11 that is surrounded by the SiO2 film 12. A gate electrode 34 is formed by patterning a P type polycrystal Si film 33 that is deposited on all surface by CVD method and a polyside layer such as WSix film 17. Therefore, characteristics between the PMOS transistor 26 and the NMOS transistor 27 that are formed subsequently are balanced and the well balanced design in terms of design rule is enabled.

公开(公告)号：JPH0737997A

公开(公告)日：1995-02-07

申请号：JP19926393

申请日：1993-07-15

Applicant: SONY CORP

Inventor： MANO MICHIO

IPC: H01L27/11 ,  H01L21/8244

Abstract: PURPOSE:To reduce the area of a memory cell and at the same time improve reliability by laying out first and second word lines so that they nearly cross first and second active regions and they correspond to each on one part of the gate electrodes of first and second driver transistors CONSTITUTION:Two first and second active regions 3 and 4 are formed in parallel to a semiconductor substrate 2 within a memory cell 1 of SRAM. A first driver transistor 7 is formed at the first active region 3 at one side in diagonal direction of the memory cell 1. Then, a second driver transistor 8 is formed at a second active region 4 at the opposite side in diagonal direction. A first word line 17 is formed in a state so that it nearly cross the first and second active regions 3 and 4 or a second word line 18 is formed on one part of a second crate electrode 14 and in a state so that it nearly crosses the first and second active regions 3 and 4.

公开(公告)号：JPH1117028A

公开(公告)日：1999-01-22

申请号：JP17151797

申请日：1997-06-27

Applicant: SONY CORP

Inventor： MANO MICHIO

IPC: H01L21/8238 ,  H01L21/8244 ,  H01L27/092 ,  H01L27/11

Abstract: PROBLEM TO BE SOLVED: To realize an SRAM which allows the cell area to be reduced and provides a stable self-aligned contacts. SOLUTION: SRAM 2 comprises a first and a second inverters composed of an NMOS and a PMOS which constitute flip flops in a memory cell 200 and n-type gate electrode wirings 4, 5 where NMOS gate electrodes 41, 42 and PMOS gate electrodes 51, 52 are continuous. A lead-out wiring 13 from the wiring 4 of the first inverter is connected to a p-type diffused layer 9 to be a second load Tr, Q4 of the second inverter through a p type buried contact part 15. Further, the leading wiring 13 has a p-type conductive film on this part 15, and seventh n-type self-aligned contact part 36 is formed near the lead-out wiring 13.

公开(公告)号：JPH1117026A

公开(公告)日：1999-01-22

申请号：JP17151697

申请日：1997-06-27

Applicant: SONY CORP

Inventor： MANO MICHIO

IPC: H01L27/11 ,  H01L21/8244

Abstract: PROBLEM TO BE SOLVED: To realize an SRAM superior in device characteristics and productivity, which allows the cell area to be reduced and a p-type diffused layer to be connected to gate electrodes, without forming p-n junctions. SOLUTION: SRAM 1 comprises flip flops each composed of a first and second inverters composed of an NMOS and PMOS on a semiconductor substrate in a memory cell 200, and n-type gate electrode wirings 4, 5 where NMOS gate electrodes 41, 42 and PMOS gate electrodes 51, 52 are continuous, and a leading wiring 13 from the wiring 4 of the first inverter is connected to a p-type diffused layer 9 to be a second load Tr, Q4 of the second inverter through a p type buried contact part 15 and is formed of a p-type conductive film on this part 15.

公开(公告)号：JPH08321610A

公开(公告)日：1996-12-03

申请号：JP12847695

申请日：1995-05-26

Applicant: SONY CORP

Inventor： MANO MICHIO

IPC: H01L21/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

Abstract: PURPOSE: To provide the title semiconductor device in such a constitution capable of simultaneously forming MISFETs not in silicide structure without increasing the number steps simultaneously with the MISFETs in the silicide structure, and a manufacturing method thereof. CONSTITUTION: Within the title semiconductor device, an element isolation insulating layer 2 with an element forming aperture part formed therein is formed, a semiconductor substrate 1 while side spacers are formed on both side faces opposing to each other in this aperture part, and a gate electrode 51 is formed of policrystalline semiconductor layer with a silicide layer 9 formed thereon so that the inside edge of the element forming aperture part opposing to both side faces may be formed extending to the contact position with the side spaces furthermore an electrode to a source and drain or a contact window of wiring layers 12 may be formed on this element isolation insulating layer 2.

公开(公告)号：JPH08222738A

公开(公告)日：1996-08-30

申请号：JP4619195

申请日：1995-02-10

Applicant: SONY CORP

Inventor： MANO MICHIO

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092

Abstract: PURPOSE: To manufacture a fine and high speed field-effect semiconductor device by a method wherein an element separating region in the narrower width to the same extent as that in a trench element separating structure by removing the element active region of an insulating film on a semiconductor substrate surface. CONSTITUTION: After the formation of an SiO2 film 35 on the whole surface of an N type Si substrate 34 by oxidizing the surface of this substrate 34, the SiO2 film 35 in the element active region is removed to leave the SiO2 film 35 on the whole separating region only. Next, an Si layer 36 having the surface about 100nm lower than the surface of the SiO2 film 35 is selectively grown on the Si substrate 34. Next, an impurity region 38 as a punch-through stopper layer is formed on the surface of the Si layer 36 further to form another Si layer 41 for the formation of a channel region. Through these procedures, the punch-through stopper layer can be formed suppressing the increase in the impurity concentration in the channel region, thereby enabling the mobility of carriers in the channel region to be increased.

公开(公告)号：JPH08186181A

公开(公告)日：1996-07-16

申请号：JP33833994

申请日：1994-12-28

Applicant: SONY CORP

Inventor： MANO MICHIO

IPC: H01L27/11 ,  H01L21/8244

Abstract: PURPOSE: To eliminate the need for a wiring exclusively for patterns and the contact part by arranging four element activates regions along a word wire between a pair of word line and extending the word line in cross direction of the word line. CONSTITUTION: Element active regions 30a-30d of four transistor 14-17 constituting a pair of inverters are isolated at an element isolation region and are successively arranged along the word lines between a pair of word lines 31c and 31d. Also, the element active regions 30a-30c are extended in a direction for crossing the word lines 31c and 31d. Therefore, by extending the gate electrodes 31a and 31b of a pair of inverters, a pair of inverters can be mutually connected. Also, the element activated regions 30a-30d can be easily arranged for the word lines 31c and 31d, the shape of the element activated regions 30a-30d and that of transistors 14-17 can be simplified.

公开(公告)号：JP2001066642A

公开(公告)日：2001-03-16

申请号：JP23779699

申请日：1999-08-25

Applicant: SONY CORP

Inventor： MANO MICHIO

IPC: G02F1/137 ,  G02F1/1339 ,  G02F1/141

Abstract: PROBLEM TO BE SOLVED: To provide a means to stably form a uniform substrate gap