公开(公告)号：JP2014160929A

公开(公告)日：2014-09-04

申请号：JP2013030402

申请日：2013-02-19

Applicant: Sony Corp ,  ソニー株式会社

Inventor： AKIBA AKIRA ,  HASHIMOTO MITSUO ,  MORITA SHINYA ,  MITARAI TAKASHI ,  TAKETOMO MIKIHIRO ,  ONIKI KAZUNAO ,  IKEDA KOICHI

IPC: H01P3/08 ,  H01R13/66 ,  H01R24/60 ,  H01R31/06

CPC classification number: H01R13/6691 ,  H01P3/08 ,  H01P3/085 ,  H01P3/121 ,  H01R13/6599 ,  H01R24/64 ,  H01R2107/00 ,  H05K1/0219 ,  H05K2201/0715 ,  H05K2201/09336 ,  H05K2201/09618

Abstract: PROBLEM TO BE SOLVED: To achieve high-quality and high-speed communication without increasing a mounting region.SOLUTION: A signal transmission cable includes a first connector, a second connector, and a cable connecting the first connector and the second connector. Each of the first connector and the second connector has at least one or more layers of organic substrates. The cable has a dielectric layer and a metal layer. The dielectric layer of the cable is formed by extending part of the organic substrates of the first connector and the second connector. A tip of the metal layer of the cable is directly connected to an output terminal of a chip disposed on the organic substrates of the first connector and the second connector.

Abstract translation: 要解决的问题：在不增加安装区域的情况下实现高质量和高速的通信。解决方案：信号传输电缆包括第一连接器，第二连接器和连接第一连接器和第二连接器的电缆。 第一连接器和第二连接器中的每一个具有至少一层或多层有机衬底。 电缆具有电介质层和金属层。 电缆的电介质层通过延伸第一连接器和第二连接器的有机衬底的一部分而形成。 电缆的金属层的尖端直接连接到设置在第一连接器和第二连接器的有机基板上的芯片的输出端子。

公开(公告)号：JP2007000961A

公开(公告)日：2007-01-11

申请号：JP2005183181

申请日：2005-06-23

Applicant: SONY CORP

Inventor： MITARAI TAKASHI ,  IKEDA KOICHI ,  TADA MASAHIRO ,  AKIBA AKIRA ,  MORITA SHINYA

IPC: B81B7/02 ,  B81C1/00

Abstract: PROBLEM TO BE SOLVED: To load the same substrate with a semiconductor element and a micro-electromechanical device by manufacturing the semiconductor element and the micro-mechanical device on the same substrate, and then forming wiring for connecting the semiconductor element and the micro-mechanical device to each other. SOLUTION: This semiconductor compound device 1 includes: a semiconductor element 21 formed on the substrate 11; an insulating film 41 formed on the substrate 11 to cover the semiconductor element 21; the micro-electromechanical device 31 formed on the insulating film 41; and a wiring layer 50 for connecting the semiconductor element 21 and the micro-electromechanical device 31 to each other. The device solves the above problem. COPYRIGHT: (C)2007,JPO&INPIT

公开(公告)号：JP2005311568A

公开(公告)日：2005-11-04

申请号：JP2004123891

申请日：2004-04-20

Applicant: Sony Corp ,  ソニー株式会社

Inventor： NANBADA KOJI ,  TANAKA NAOHIRO ,  TADA MASAHIRO ,  MITARAI TAKASHI

IPC: H03H9/46 ,  H03H9/24

Abstract: PROBLEM TO BE SOLVED: To provide a filter device for developing a filtering function equivalent to that of a band-pass filter, without mutual mechanical connecting the beam electrodes of two minute resonators. SOLUTION: A plurality of minute resonators 15, 16, 17, 18 are electrically interconnected in a lattice form among two input terminals for balanced input and two output terminals for balanced output, by respectively connecting the minute resonator 15 (16), each having a beam structure in series between the input terminal 11 (12) and the output terminal 13 (14) and by respectively connecting the minute resonator 17 (18), each having a beam structure in series in between the input terminal 11 (12) and the output terminal 14 (13). COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于开发与带通滤波器相当的滤波功能的滤波器装置，而无需相互机械连接两分钟谐振器的波束电极。 解决方案：通过分别连接微谐振器15（16）和微分谐振器15（16），多个微分谐振器15,16,17,18以平衡输入的两个输入端和平衡输出的两个输出端之间以格子形式电互连， 每个都具有串联在输入端子11（12）和输出端子13（14）之间的梁结构，并且通过分别连接微小谐振器17（18），每个谐振器17（18）串联在输入端子11（12 ）和输出端子14（13）。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2002368200A

公开(公告)日：2002-12-20

申请号：JP2001174089

申请日：2001-06-08

Applicant: Sony Corp ,  ソニー株式会社

Inventor： MITARAI TAKASHI ,  NAGAHAMA TSUTOMU ,  KATORI KENJI

IPC: G11C11/404 ,  G11C11/22 ,  H01L21/8246 ,  H01L27/105

CPC classification number: G11C11/22

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory device of the so-called 'stack capacitor structure', which has a structure capable of reliably preventing peeling-off of a lower electrode. SOLUTION: The semiconductor memory device comprises (A) a transistor, (B) a capacitor section provided on the upper part of the transistor via an interlayer insulating layer 16 and consisting of a lower electrode 31, a capacitor layer 32 formed of a high dielectric material or a ferroelectric material and an upper electrode 33, (C) a contact plug 21, (D) a diffusion barrier layer 23, and (E) an adhesive layer 30 provided between at least the electrode 31 and the layer 23; the layer 30 contains a noble metallic element as the principal component, and further contains a metal element excepting the noble metallic material, an alkali element and an alkali rare-earth metal as an component, and consists of an alloy which does not contain an oxygen element.

Abstract translation: 要解决的问题：提供具有能够可靠地防止下部电极的剥离的结构的所谓的“堆叠电容器结构”的半导体存储器件。 解决方案：半导体存储器件包括（A）晶体管，（B）经由层间绝缘层16设置在晶体管的上部的电容器部分，由下电极31，由高电介质形成的电容器层32 材料或铁电材料和上电极33，（C）接触塞21，（D）扩散阻挡层23和（E）至少设置在电极31和层23之间的粘合剂层30; 层30包含贵金属元素作为主要成分，并且还含有作为成分的贵金属材料，碱金属元素和碱性稀土金属以外的金属元素，并且由不含氧的合金构成 元件。

公开(公告)号：JP2011258654A

公开(公告)日：2011-12-22

申请号：JP2010130266

申请日：2010-06-07

Applicant: Sony Corp ,  ソニー株式会社

Inventor： AKIBA AKIRA ,  MORITA SHINYA ,  IKEDA KOICHI ,  MITARAI TAKASHI

IPC: H01L23/12 ,  H01L23/14 ,  H01L25/00

CPC classification number: H01L2223/6677 ,  H01L2224/16225 ,  H01L2924/1461 ,  H01L2924/1515 ,  H01L2924/15159 ,  H01L2924/157 ,  H01L2924/19107 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an interposer which exhibits excellent high frequency characteristics while simplifying the manufacturing process.SOLUTION: A through electrode 12 is provided through a substrate 11, a dielectric layer 14A is formed on the substrate 11 and then interconnections 16A and 16B and an antenna 17 are formed on the dielectric layer 14A. Subsequently, dielectric layers 14 and 14C are laminated, respectively, on the undersurface of the substrate 11 and on the dielectric layer 14A, and a recess 19A is provided in the substrate 11 thus completing an interposer 10A. After bonding a semiconductor chip 20 to the top face side of the substrate 11, the undersurface side of the substrate 11 is mounted on a printed board 30. Since the interconnections 16A and 16B for connecting the semiconductor chip 20 and the printed board 30 are provided on the substrate 11, the manufacturing process is simplified.

Abstract translation: 要解决的问题：提供一种显示出优异的高频特性同时简化制造过程的中介层。 解决方案：通过基板11设置贯通电极12，在基板11上形成电介质层14A，然后在电介质层14A上形成布线16A，16B和天线17。 随后，电介质层14和14C分别层叠在基板11的下表面和电介质层14A上，并且在基板11中设置凹部19A，从而完成插入件10A。 在将半导体芯片20接合到基板11的顶面侧之后，将基板11的下表面侧安装在印刷电路板30上。由于设置用于连接半导体芯片20和印刷电路板30的互连16A和16B 在基板11上，简化了制造工艺。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2011114719A

公开(公告)日：2011-06-09

申请号：JP2009270760

申请日：2009-11-27

Applicant: Sony Corp ,  ソニー株式会社

Inventor： SOTOZAKI MINEHIRO ,  MORITA SHINYA ,  MITARAI TAKASHI

IPC: H01P3/08 ,  H01P11/00 ,  H01Q23/00

Abstract: PROBLEM TO BE SOLVED: To provide a high-frequency device capable of suppressing reduction of high-frequency characteristics of a high-frequency device having openings on a substrate. SOLUTION: On a substrate 11, a dielectric layer 15A, high-frequency element 16s (slot antenna 16A, microstrip line 16B), a dielectric layer 15B and an RFIC circuit 18 are formed in order. Openings 17 (17A, 17B) are provided in the substrate 11 located opposite to the high-frequency elements 16 (slot antenna 16A, microstrip line 16B). On the dielectric layer 15, complementing layers 21 (21A, 21b) constituted of dielectric materials or magnetic materials are provided in positions opposed to the openings 17 (17A, 17B). Thus, reduction of a dielectric constant or permeability caused by forming the openings 17 is complemented in the substrate 11and reduction of high-frequency characteristics of a high-frequency device 1 can be suppressed. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 解决的问题：提供能够抑制在基板上具有开口的高频装置的高频特性的降低的高频装置。 解决方案：在基板11上依次形成电介质层15A，高频元件16s（狭缝天线16A，微带线16B），电介质层15B和RFIC电路18。 开口17（17A，17B）设置在与高频元件16（缝隙天线16A，微带线16B）相对的基板11中。 在电介质层15上，与开口17（17A，17B）相对的位置设置有由电介质材料或磁性材料构成的互补层21（21A，21b）。 因此，在基板11中补充了由形成开口17引起的介电常数或导磁率的降低，并且可以抑制高频装置1的高频特性的降低。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2008012631A

公开(公告)日：2008-01-24

申请号：JP2006186857

申请日：2006-07-06

Applicant: Sony Corp ,  ソニー株式会社

Inventor： TADA MASAHIRO ,  KINOSHITA TAKASHI ,  MITARAI TAKASHI

IPC: B81B3/00 ,  B81C1/00 ,  H01P1/12

Abstract: PROBLEM TO BE SOLVED: To provide an electric machine element which can reduce a gap length between a lower electrode and an upper electrode of a movable element thereof.
SOLUTION: The electric machine element is composed of the movable element 25 having the lower electrode 23 and the upper electrode via a space 24 therebetween, and either one or both of the lower electrode 23 and the upper electrode 25 are formed of a laminated structure.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种能够减小其可动元件的下电极和上电极之间的间隙长度的电机元件。 解决方案：电机元件由具有下电极23和上电极的可移动元件25经由其间的空间24组成，并且下电极23和上电极25中的一个或两者由 层压结构。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007134453A

公开(公告)日：2007-05-31

申请号：JP2005325009

申请日：2005-11-09

Applicant: Sony Corp ,  ソニー株式会社

Inventor： MITARAI TAKASHI ,  IKEDA KOICHI

IPC: H01L23/14 ,  B81B3/00 ,  B81B7/02 ,  B81C1/00

Abstract: PROBLEM TO BE SOLVED: To form a cavity wherein a micro machine surely operates, without damaging the reliability of an electronic circuit.
SOLUTION: A micro machine operation structure 7 is arranged in an opening 12a for etching which is formed in a wiring interlayer insulating layer 9, and an etching stop layer 4 is arranged under the micro machine operation structure 7. An etching protection wall 12 is formed on the inside wall surface of the opening 12a in the wiring interlayer insulating layer 9 at a necessary clearance with the micro machine operation structure 7, and a cavity 13 is formed in the arrangement portion of the micro machine operation structure 7 so as to keep its entire outer surface not being in contact with the other part. Thus, the deterioration of characteristic in an adjacent wiring due to the formation of the cavity 13 is avoided by the etching protection wall 12.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：形成微型机器可靠地工作的腔体，而不损害电子电路的可靠性。 解决方案：微机操作结构7设置在形成在布线层间绝缘层9中的用于蚀刻的开口12a中，并且在微机操作结构7下方布置有蚀刻停止层4.蚀刻保护壁 12以与微机操作结构7必需的间隙形成在布线层间绝缘层9中的开口12a的内壁面上，并且在微机操作结构7的配置部分中形成空腔13，以便 以保持其整个外表面不与另一部分接触。 因此，通过蚀刻保护壁12避免了由于形成空腔13而在相邻布线中的特性劣化。版权所有：（C）2007，JPO＆INPIT

公开(公告)号：JP2005342817A

公开(公告)日：2005-12-15

申请号：JP2004163053

申请日：2004-06-01

Applicant: Sony Corp ,  ソニー株式会社

Inventor： MITARAI TAKASHI ,  TANAKA NAOHIRO ,  TADA MASAHIRO ,  NANBADA KOJI ,  AISAKA TSUTOMU

IPC: B81C1/00 ,  H01L41/09 ,  H01L41/18 ,  H01L41/187 ,  H01L41/22 ,  H03H3/02 ,  H03H9/17

Abstract: PROBLEM TO BE SOLVED: To manufacture a hollow structure element having high durability by preventing the first and secondary stictions. SOLUTION: A structure 2 is provided through a sacrifice layer imbedded in a recessed portion 10a provided on a base plate 10, and a hollow structure element 1 structures a hollow space S in the recessed portion 10a by etching the sacrifice layer. On an inner surface of the recessed portion 10a, a thin film 11 made from material capable of forming a predetermined product by reacting with etchant etching the sacrifice layer is provided. The manufacturing method forms the thin film 11 made from the material capable of forming the predetermined product by reacting with the etchant etching the sacrifice layer on the inner surface of the recessed portion 10a, after forming the recessed portion 10a on the base plate 10, and imbeds the sacrifice layer through the thin film 11. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：通过防止第一和第二结构来制造具有高耐久性的中空结构元件。 解决方案：结构2通过埋设在设置在基板10上的凹部10a中的牺牲层提供，中空结构元件1通过蚀刻牺牲层来构造凹部10a中的中空空间S. 在凹部10a的内表面上，设置由蚀刻牺牲层的蚀刻剂反应形成预定产品的材料制成的薄膜11。 制造方法形成由能够形成预定产品的材料制成的薄膜11，在形成基板10上的凹部10a之后，与蚀刻剂蚀刻凹部10a的内表面上的牺牲层反应， 通过薄膜11掩盖牺牲层。版权所有（C）2006年，JPO＆NCIPI

公开(公告)号：JP2004241690A

公开(公告)日：2004-08-26

申请号：JP2003030838

申请日：2003-02-07

Applicant: Oki Electric Ind Co Ltd ,  Sony Corp ,  ソニー株式会社 ,  沖電気工業株式会社

Inventor： IGARASHI YASUSHI ,  MITARAI TAKASHI ,  NAGAHAMA TSUTOMU

IPC: H01L27/105 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a stacked cell which has a constitution suitable for the high integration and fining of a semiconductor memory device and has a constitution for preventing the oxidation of a plug in a manufacturing process of the cell, and to provide a manufacturing method of the cell.
SOLUTION: The stacked cell 100 comprises an insulating film 12, a plug 114 provided through the insulating film 12, a lower electrode 18 provided to the upper side of the insulating film 12 and electrically combined with the plug 114, an anti-plug oxygen ingression preventing film 102 provided as a foundation film of the lower electrode 18 between the lower electrode 18 and the insulating film 12, and a dielectric film 120 and an upper electrode 22 laminated on the lower electrode 18 one by one.
COPYRIGHT: (C)2004,JPO&NCIPI