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公开(公告)号：JPH11261015A
公开(公告)日：1999-09-24
申请号：JP702699
申请日：1999-01-13
Applicant: ST MICROELECTRONICS INC
Inventor： KALNITSKY ALEXANDER , KRAMER ALAN , FABBRIZIO VITO , GOZZINI GIOVANNI , GUPTA BHUSAN , SABARINI MARCO
IPC: H01G7/00 , G01B7/28 , G01L9/00 , G01P15/08 , G01P15/125 , H01L21/822 , H01L27/04
Abstract: PROBLEM TO BE SOLVED: To integrate a variable capacitor in a semiconductor device through the use of regular manufacturing technology and substance, by constructing a stacked constitution body having a dielectric membrane which can be moved in fixed plates that are mutually detached and in a space between the plates, namely, in a gap. SOLUTION: A variable capacitor has a flexible membrane 14 and it exists on a lower side containing a first conductor 18 which is parallel to a second conductor 20 and is detached from it. The flexible membrane 14 is dielectric substance and is composed of silicon nitride. The flexible membrane 14 has a peripheral part 32 and the peripheral part 32 is supported by a semiconductor substrate 24 through an intermediate layer. The membrane 14 has a beam 36 which partially extends into a gap 22 between the first and second conductors 18 and 20. The membrane 14 has flexibility and can freely move in the gap 22. The beam 36 extends downward in the gap 22 and it is abutted on the upper face of a nitride layer 30.
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公开(公告)号：JP2000036586A
公开(公告)日：2000-02-02
申请号：JP17842599
申请日：1999-06-24
Applicant: ST MICROELECTRONICS INC
Inventor： KALNITSKY ALEXANDER , BRYANT FRANK R , SABATINI MARCO
IPC: H01L27/14 , H01L27/146 , H01L31/0352 , G01J1/44 , H04N5/335
Abstract: PROBLEM TO BE SOLVED: To increase the optical filter of the pixel of a CMOS image array by providing a radiation-sensitive resistance element where an access transistor being located at a second level is connected to an access transistor being located at a second level. SOLUTION: The pixel of a passive-type pixel construct 300 has a substrate 301, and an MOS pass transistor 303 is formed on it. The transistor is provided with a source being formed in the substrate, drain diffusion regions 305 and 307, and a gate 308 being formed on the substrate. In a gate electrode, first and second capacitor plates 309 and 311 of two polysilicon constructs are provided at the upper part of the pass transistor 303. The first capacitor plate 309 is separated from the substrate 301 and the pass transistor 303 by a passivation layer 313. The second capacitor plate 311 is separated from the first capacitor plate 309 by a capacitor dielectric layer 315. A photosensitive resistance element 317 is provided in the inclusion layer of the second capacitor plate.
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公开(公告)号：DE69230514D1
公开(公告)日：2000-02-10
申请号：DE69230514
申请日：1992-07-30
Applicant: ST MICROELECTRONICS INC
Inventor： KALNITSKY ALEXANDER
IPC: H01L21/28 , H01L21/302 , H01L21/74 , H01L21/768
Abstract: A method is provided for forming a polysilicon buried contact of an integrated circuit, and an integrated circuit formed according to the same. A field oxide region is formed over a portion of a substrate leaving an exposed active region. An oxide layer is formed over the active region. A first photoresist layer is formed and patterned over the first silicon layer. The first silicon layer is then etched to form an opening therethrough to expose a portion of the oxide layer. The oxide layer is etched through the opening to expose a portion of the substrate. a conductive etch stop layer is formed over the exposed portion of the substrate and the first photoresist layer. The first photoresist layer and the etch stop layer overlying the first photoresist layer are then removed. A second silicon layer is formed over the first silicon layer and the remaining etch stop layer. A second photoresist layer is formed and patterned over the second silicon layer. The first and second silicon layers are then etched to form a conductive structure contacting the exposed portion of the substrate through the etch stop layer.
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公开(公告)号：DE69820551T2
公开(公告)日：2004-11-04
申请号：DE69820551
申请日：1998-09-10
Applicant: ST MICROELECTRONICS INC
Inventor： KALNITSKY ALEXANDER , KRAMER ALAN
Abstract: A planar fingerprint pattern detecting array includes a large number of individual skin-distance sensing cells that are arranged in a row/column configuration. Each sensing cell includes an amplifier having an ungrounded input mode and an ungrounded output node. Output-to-input negative feedback that is sensitive to the fingerprint pattern is provided for each amplifier by way of (1) a first capacitor plate that is placed vertically under the upper surface of a dielectric layer and is connected to the ungrounded amplifier input node, (2) a second capacitor plate that is placed vertically under the upper surface of the dielectric layer in close horizontal spatial relation to the first capacitor plate and is connected to the ungrounded output node, and (3) an ungrounded fingertip whose fingerprint pattern is to be detected, which ungrounded fingertip is placed on the upper surface of the dielectric layer in close vertical spatial relation with the first and second capacitor plates. Electrostatic discharge protection relative to electrostatic potential that may be carried by the ungrounded fingertip is provided by placing a number of grounded metal paths within the dielectric layer to spatially surround each of the first and second capacitor plates, this being done in a manner that does not disturb the ungrounded state of the fingertip.
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公开(公告)号：DE69919235D1
公开(公告)日：2004-09-16
申请号：DE69919235
申请日：1999-01-12
Applicant: ST MICROELECTRONICS INC
Inventor： KALNITSKY ALEXANDER , KRAMER ALAN , FABBRIZIO VITO , GOZZINI GIOVANNI , GUPTA BHUSAN , SABARINI MARCO
IPC: H01G7/00 , G01B7/28 , G01L9/00 , G01P15/08 , G01P15/125 , H01L21/822 , H01L27/04 , G01L9/12
Abstract: A variable capacitor in a semiconductor device is described in which the capacitance is varied by the movement of a dielectric material in the space between the plates of the capacitor in response to an external stimulus. A method of making such a variable capacitor is also described in which the capacitor is built in a layered structure with the top layer including a portion of dielectric material extending into the space between the capacitor plates. After formation of the top layer, an intermediate layer is etched away to render the top layer flexible to facilitate movement of the dielectric material in the space between the capacitor plates.
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Patent Agency Ranking
公开(公告)号：DE69919235T2
公开(公告)日：2005-09-08
申请号：DE69919235
申请日：1999-01-12
Applicant: ST MICROELECTRONICS INC
Inventor： KALNITSKY ALEXANDER , KRAMER ALAN , FABBRIZIO VITO , GOZZINI GIOVANNI , GUPTA BHUSAN , SABARINI MARCO
IPC: H01G7/00 , G01B7/28 , G01L9/00 , G01P15/08 , G01P15/125 , H01L21/822 , H01L27/04 , G01L9/12
Abstract: A variable capacitor in a semiconductor device is described in which the capacitance is varied by the movement of a dielectric material in the space between the plates of the capacitor in response to an external stimulus. A method of making such a variable capacitor is also described in which the capacitor is built in a layered structure with the top layer including a portion of dielectric material extending into the space between the capacitor plates. After formation of the top layer, an intermediate layer is etched away to render the top layer flexible to facilitate movement of the dielectric material in the space between the capacitor plates.
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公开(公告)号：DE69825367T2
公开(公告)日：2005-08-04
申请号：DE69825367
申请日：1998-06-30
Applicant: ST MICROELECTRONICS INC
Inventor： KALNITSKY ALEXANDER , KRAMER ALAN
Abstract: A planar, capacitive-type, rectangular, and multi-pixel fingerprint sensing array is mounted on the horizontal and generally rectangular top-surface of a dome that extends upward generally from the center of a horizontally disposed and generally rectangular silicon substrate member. The dome is formed by four upward extending and inclined, or tapered, side wall surfaces, at least one wall surface of which carries electrical circuit paths that electrically connected to the various circuit elements of the sensing array. A generally rectangular, encircling and wall-like card carrier assembly includes a generally horizontal upper-surface having a generally centered opening through which only the dome and sensing array project upward. The bottom-surface of the card carrier assembly is mounted to edge portions of the silicon substrate member in a manner to surround and protect all but the upward extending dome. A flexible membrane or laminate is sealed to the top-surface of the card carrier assembly to form a flexible surface over the sensing array. The card carrier assembly includes circuit path having an external portion and having an internal portion that connects to the wall-mounted internal electrical circuit paths, the external portion providing external connection to the internal sensing array.
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公开(公告)号：DE69825367D1
公开(公告)日：2004-09-09
申请号：DE69825367
申请日：1998-06-30
Applicant: ST MICROELECTRONICS INC
Inventor： KALNITSKY ALEXANDER , KRAMER ALAN
Abstract: A planar, capacitive-type, rectangular, and multi-pixel fingerprint sensing array is mounted on the horizontal and generally rectangular top-surface of a dome that extends upward generally from the center of a horizontally disposed and generally rectangular silicon substrate member. The dome is formed by four upward extending and inclined, or tapered, side wall surfaces, at least one wall surface of which carries electrical circuit paths that electrically connected to the various circuit elements of the sensing array. A generally rectangular, encircling and wall-like card carrier assembly includes a generally horizontal upper-surface having a generally centered opening through which only the dome and sensing array project upward. The bottom-surface of the card carrier assembly is mounted to edge portions of the silicon substrate member in a manner to surround and protect all but the upward extending dome. A flexible membrane or laminate is sealed to the top-surface of the card carrier assembly to form a flexible surface over the sensing array. The card carrier assembly includes circuit path having an external portion and having an internal portion that connects to the wall-mounted internal electrical circuit paths, the external portion providing external connection to the internal sensing array.
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公开(公告)号：DE69820551D1
公开(公告)日：2004-01-29
申请号：DE69820551
申请日：1998-09-10
Applicant: ST MICROELECTRONICS INC
Inventor： KALNITSKY ALEXANDER , KRAMER ALAN
Abstract: A planar fingerprint pattern detecting array includes a large number of individual skin-distance sensing cells that are arranged in a row/column configuration. Each sensing cell includes an amplifier having an ungrounded input mode and an ungrounded output node. Output-to-input negative feedback that is sensitive to the fingerprint pattern is provided for each amplifier by way of (1) a first capacitor plate that is placed vertically under the upper surface of a dielectric layer and is connected to the ungrounded amplifier input node, (2) a second capacitor plate that is placed vertically under the upper surface of the dielectric layer in close horizontal spatial relation to the first capacitor plate and is connected to the ungrounded output node, and (3) an ungrounded fingertip whose fingerprint pattern is to be detected, which ungrounded fingertip is placed on the upper surface of the dielectric layer in close vertical spatial relation with the first and second capacitor plates. Electrostatic discharge protection relative to electrostatic potential that may be carried by the ungrounded fingertip is provided by placing a number of grounded metal paths within the dielectric layer to spatially surround each of the first and second capacitor plates, this being done in a manner that does not disturb the ungrounded state of the fingertip.
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公开(公告)号：DE69230514T2
公开(公告)日：2000-06-21
申请号：DE69230514
申请日：1992-07-30
Applicant: ST MICROELECTRONICS INC
Inventor： KALNITSKY ALEXANDER
IPC: H01L21/28 , H01L21/302 , H01L21/74 , H01L21/768
Abstract: A method is provided for forming a polysilicon buried contact of an integrated circuit, and an integrated circuit formed according to the same. A field oxide region is formed over a portion of a substrate leaving an exposed active region. An oxide layer is formed over the active region. A first photoresist layer is formed and patterned over the first silicon layer. The first silicon layer is then etched to form an opening therethrough to expose a portion of the oxide layer. The oxide layer is etched through the opening to expose a portion of the substrate. a conductive etch stop layer is formed over the exposed portion of the substrate and the first photoresist layer. The first photoresist layer and the etch stop layer overlying the first photoresist layer are then removed. A second silicon layer is formed over the first silicon layer and the remaining etch stop layer. A second photoresist layer is formed and patterned over the second silicon layer. The first and second silicon layers are then etched to form a conductive structure contacting the exposed portion of the substrate through the etch stop layer.
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