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    1.
    发明专利
    未知

    公开(公告)号：DE602006006990D1

    公开(公告)日：2009-07-09

    申请号：DE602006006990

    申请日：2006-06-28

    Applicant: ST MICROELECTRONICS NV ,  ST MICROELECTRONICS SRL

    Inventor： PAPPALARDO FRANCESCO ,  NOTARANGELO GIUSEPPE ,  SALURSO ELENA ,  GUIDETTI ELIO

    IPC: G06F9/38

    Abstract: A processor architecture (10) e.g. for multimedia applications, includes a plurality of processor clusters (18a, 18b) that provide a vectorial data processing capability. The processing elements in the processor clusters (18a, 18b) are configured to process both data with a given bit length N and data with bit lengths N/2, N/4, and so on according to a Single Instruction Multiple Data (SIMD) paradigm. A load unit (26) is provided for loading into the processor clusters (18a, 18b) data to be processed in the form of sets of more significant bits and less significant bits of operands to be processed according to a same instruction. An intercluster datapath (28) exchanges and/or merges data between the processor clusters (18a, 18b). The intercluster datapath (28) is scalable to activate selected ones of the processor clusters (18a, 18b), whereby the architecture (10) is adapted to operate simultaneously on SIMD, scalar and vectorial data. Preferably, the instruction subsystem (12) has instruction parallelism capability and the intercluster datapath (28) is configured for performing operations on e.g. 2*N data. Preferably, a data cache memory (34) is provided which is accessible either in a scalar mode or in a vectorial mode.

    3.
    发明专利
    未知

    公开(公告)号：DE60209690D1

    公开(公告)日：2006-05-04

    申请号：DE60209690

    申请日：2002-09-25

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PAPPALARDO FRANCESCO ,  NOTARANGELO GIUSEPPE

    IPC: G06F13/42 ,  G06F13/40

    Abstract: The process involves verifying recurrence of condition in which transmission on bus in non-encoded and encoded formats gives an identical switching activity on the bus for digital signals at a given instant. The transmission causes the additional signal associated with the signal to be transmitted at another instant to keep its logic value with respect to logic value assumed by additional signal for preceding instant. Independent claims are also included for the following: (1) an encoder for transmitting digital signals at given instants on a bus (2) a decoder for receiving digital signals transmitted on a bus (3) a computer program product directly loadable into memory of a computer and comprising a software code portions for implementing digital signal transmitting process.

    4.
    发明专利
    未知

    公开(公告)号：DE60322540D1

    公开(公告)日：2008-09-11

    申请号：DE60322540

    申请日：2003-10-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PAPPALARDO FRANCESCO ,  NOTARANGELO GIUSEPPE ,  VISALLI GIUSEPPE

    IPC: H04L25/49 ,  H04B10/50 ,  H04B10/516 ,  H04B10/80

    Abstract: In a method for transmitting on an optical connection (16) a sequence of input data (b(t)) comprising first ("1") and second ("0") logic states, there is envisaged the operation of providing an optical source (15) for generating an optical signal to be transmitted on said optical connection (16), said optical source (15) being able to generate optical pulses at the occurrence of said first ("1") logic states. The method comprises the operation of: - encoding (470,570) said sequence of input data (b(t)) in an encoded sequence of data (B(t)) prior to transmission on said optical connection (16), where said encoding operation minimizes the first logic states ("1") in said encoded sequence of data (B(t)). A preferential application is to optical-fibre communication systems with on-chip integrated buses.

    6.
    发明专利
    未知

    公开(公告)号：DE60221396D1

    公开(公告)日：2007-09-06

    申请号：DE60221396

    申请日：2002-09-25

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PAPPALARDO FRANCESCO ,  NOTARANGELO GIUSEPPE

    IPC: G06F13/42 ,  G06F13/40

    Abstract: The process involves comparing bit by bit in orderly sequence to identify a set of bits that are not changed and another set of bits that are changed in context of a signal to be transmitted on a bus at an instant and preceding instant. Transmission of signal bus in non-encoded format and in encoded format, and the limitation of bits are decided. Independent claims are also included for the following: (1) an encoder for transmitting digital signals at given instants on a bus (2) a decoder for receiving digital signals transmitting on a bus (3) a computer program product directly loadable into the memory of a computer and comprising a software code portions for implementing digital signal transmitting process.

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