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公开(公告)号:DE602006016256D1
公开(公告)日:2010-09-30
申请号:DE602006016256
申请日:2006-06-28
Applicant: ST MICROELECTRONICS NV , ST MICROELECTRONICS SRL
Inventor: PAPPALARDO FRANCESCO , NOTARANGELO GIUSEPPE , SALURSO ELENA , GUIDETTI ELIO
IPC: G06F12/08 , G06F12/084 , G06F12/0886
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公开(公告)号:DE602006006990D1
公开(公告)日:2009-07-09
申请号:DE602006006990
申请日:2006-06-28
Applicant: ST MICROELECTRONICS NV , ST MICROELECTRONICS SRL
Inventor: PAPPALARDO FRANCESCO , NOTARANGELO GIUSEPPE , SALURSO ELENA , GUIDETTI ELIO
IPC: G06F9/38
Abstract: A processor architecture (10) e.g. for multimedia applications, includes a plurality of processor clusters (18a, 18b) that provide a vectorial data processing capability. The processing elements in the processor clusters (18a, 18b) are configured to process both data with a given bit length N and data with bit lengths N/2, N/4, and so on according to a Single Instruction Multiple Data (SIMD) paradigm. A load unit (26) is provided for loading into the processor clusters (18a, 18b) data to be processed in the form of sets of more significant bits and less significant bits of operands to be processed according to a same instruction. An intercluster datapath (28) exchanges and/or merges data between the processor clusters (18a, 18b). The intercluster datapath (28) is scalable to activate selected ones of the processor clusters (18a, 18b), whereby the architecture (10) is adapted to operate simultaneously on SIMD, scalar and vectorial data. Preferably, the instruction subsystem (12) has instruction parallelism capability and the intercluster datapath (28) is configured for performing operations on e.g. 2*N data. Preferably, a data cache memory (34) is provided which is accessible either in a scalar mode or in a vectorial mode.
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公开(公告)号:JPH11312083A
公开(公告)日:1999-11-09
申请号:JP36528898
申请日:1998-12-22
Applicant: ST MICROELECTRONICS SRL
Inventor: PAPPALARDO FRANCESCO , TESI DAVIDE , MAMMOLITI FRANCESCO NINO , BOMBACI FRANCESCO
Abstract: PROBLEM TO BE SOLVED: To obtain a processor for extending an instruction set, semiconductor circuit, processor, and instruction processing method. SOLUTION: A processor is generally provided with one set of instructions formed of an operation part S1 and an operand part 82. The operand part S2 indicates the operation control signal of the processor related with at least one instruction. Thus, the instruction set can be extended so as to be suited to a request from a user himself or herself. Therefore, a processor controller receives one instruction, connects the output with the input, and transfers such an inside operation control signal without interpreting it.
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公开(公告)号:DE602004018260D1
公开(公告)日:2009-01-22
申请号:DE602004018260
申请日:2004-02-06
Applicant: ST MICROELECTRONICS SRL
Inventor: RIMI FRANCESCO , SERRATORE ALBERTO , AVELLONE GIUSEPPE , PAPPALARDO FRANCESCO , GALLUZZO AGOSTINO
IPC: H04B1/707
Abstract: In order to perform, according to a received signal (r), a channel-estimation procedure and a cell-search procedure in cellular communication systems, there are executed at least one first operation of correlation of said received signal (r) with secondary synchronization codes (SSC) and a second operation of correlation of said received signal (r) with known midamble codes (mid, MPL, MPS), whilst said channel-estimation procedure comprises a third operation of correlation of at least part of said received signal (r) with known midamble codes (mid, MPL, MPS), said first, second, and third correlation operation being executed by sending at least part (emidamble) of said received signal (r) to an input of a correlation bank (111, 151; 203, 253; 303). There are envisaged the operations of: sending, in a first time interval, the received signal (r) to said correlation bank (303) for executing the first operation of correlation of said received signal (r) with secondary synchronization codes (SSC); sending, in a second time interval, at least part (emidamble) of said received signal (r) to said same correlation bank (303) for executing the second operation of correlation of said received signal (r) with known midamble codes (mid, MPL, MPS); sending, in a second time interval, the received signal (r) to said same correlation bank (303) for executing the third operation of correlation of at least part (emidamble) of said received signal (r) with known midamble codes (mid, MPL, MPS). Preferential application is in mobile communication systems based upon standards such as UMTS, CDMA2000, IS95 or WBCDMA.
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公开(公告)号:DE60306895T2
公开(公告)日:2007-02-01
申请号:DE60306895
申请日:2003-05-07
Applicant: ST MICROELECTRONICS SRL
Inventor: PAPPALARDO FRANCESCO , VISALLI GIUSEPPE
IPC: H04B10/524 , H04L25/49
Abstract: A data stream (b(t)) including high ("1") and low ("0") logical states is transmitted over an optical link (16) by means of an optical source (15) adapted to be driven (14) via said the data stream to generate an optical signal for transmission over the optical link (16). The optical signal includes optical pulses generated at the occurrence of high logical ("1") states in said data stream (b(t)). The input data stream (b(t)) is coded (2000) into a coded data stream (B(t)) prior to the transmission over the optical link (16). The coding step minimises the logical high states ("1") in the coded data stream (B(t)), and the optical source (15) is driven by means of the coded data stream (B(t)) wherein the number of logical high states ("1") has been minimised.
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公开(公告)号:DE60210438D1
公开(公告)日:2006-05-18
申请号:DE60210438
申请日:2002-07-10
Applicant: ST MICROELECTRONICS SRL
Inventor: VISALLI GIUSEPPE , PAPPALARDO FRANCESCO
IPC: G06F13/42
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公开(公告)号:IT1318951B1
公开(公告)日:2003-09-19
申请号:ITMI20002124
申请日:2000-10-02
Applicant: ST MICROELECTRONICS SRL
Inventor: PAPPALARDO FRANCESCO , GIACALONE BIAGIO
IPC: G06N7/04
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公开(公告)号:ITRM20030012D0
公开(公告)日:2003-01-14
申请号:ITRM20030012
申请日:2003-01-14
Applicant: ST MICROELECTRONICS SRL
Inventor: PAPPALARDO FRANCESCO , PENNISI AGATINO
Abstract: There is described a method that makes it possible to transmit n binary signals through a bus of m leads, where m
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公开(公告)号:DE602005023273D1
公开(公告)日:2010-10-14
申请号:DE602005023273
申请日:2005-04-29
Applicant: ST MICROELECTRONICS SRL
Inventor: VISALLI GIUSEPPE , PAPPALARDO FRANCESCO
IPC: G06F12/10 , G06F12/08 , G06F12/0895 , G06F12/1045
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公开(公告)号:DE60325163D1
公开(公告)日:2009-01-22
申请号:DE60325163
申请日:2003-09-15
Applicant: ST MICROELECTRONICS SRL
Inventor: AVELLONE GIUSEPPE , RIMI FRANCESCO , PAPPALARDO FRANCESCO , GALLUZZO AGOSTINO , VISALLI GIUSEPPE
IPC: H04B1/707
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