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8 records (took 0.023 seconds)

    1.
    发明专利
    未知

    公开(公告)号：FR2824683B1

    公开(公告)日：2003-10-24

    申请号：FR0106139

    申请日：2001-05-09

    Applicant: ST MICROELECTRONICS SA

    Inventor： ALOFS THOMAS

    IPC: H03K3/037 ,  H03K17/00 ,  H03K17/693 ,  H03K3/3562

    Abstract: A multiplexed flip-flop electronic device includes a decoder logic circuit for providing a first switching signal, and a control circuit for receiving a clock signal and for providing a gated clock signal forming a second switching signal. The electronic device further includes a multiplexing circuit having N inputs and an output, and a flip flop circuit. The flip-flop circuit includes a first switching stage connected between the N inputs and the output of the multiplexing circuit, and includes N switches being individually controlled by the first switching signal. A first buffer stage is connected to the output of the multiplexing circuit, and a second switching stage is connected to an output of the first buffer stage. The second switching stage is controlled by the second switching signal. A second buffer stage is connected to an output of the second switching stage.

    2.
    发明专利
    未知

    公开(公告)号：DE69930235D1

    公开(公告)日：2006-05-04

    申请号：DE69930235

    申请日：1999-05-03

    Applicant: ST MICROELECTRONICS SA

    Inventor： ALOFS THOMAS ,  GROSSIER NICOLAS

    IPC: G11C8/00 ,  G11C8/18

    Abstract: A circuit for controlling the storage of data in a memory element has: a) a bistable device (22) having a first input for receiving an address input (24) and a second input (26) for receiving a clock signal; and b) circuitry (30) for receiving the output of the bistable device (22) and the clock signal (26) and providing a write enable signal for said memory, the circuitry being arranged so that the write enable signal is enabled in response to a first transition in the clock signal from a first state to a second state and disabled in response to the clock signal making the next transition back to the first state, said first and next transitions being in the same clock cycle.

    5.
    发明专利
    未知

    公开(公告)号：FR2824683A1

    公开(公告)日：2002-11-15

    申请号：FR0106139

    申请日：2001-05-09

    Applicant: ST MICROELECTRONICS SA

    Inventor： ALOFS THOMAS

    IPC: H03K3/037 ,  H03K17/00 ,  H03K17/693 ,  H03K3/3562

    Abstract: A multiplexed flip-flop electronic device includes a decoder logic circuit for providing a first switching signal, and a control circuit for receiving a clock signal and for providing a gated clock signal forming a second switching signal. The electronic device further includes a multiplexing circuit having N inputs and an output, and a flip flop circuit. The flip-flop circuit includes a first switching stage connected between the N inputs and the output of the multiplexing circuit, and includes N switches being individually controlled by the first switching signal. A first buffer stage is connected to the output of the multiplexing circuit, and a second switching stage is connected to an output of the first buffer stage. The second switching stage is controlled by the second switching signal. A second buffer stage is connected to an output of the second switching stage.

    DISPOSITIF DE GENERATION DE SUIVI DE BRANCHEMENT POUR MICROPROCESSEUR ET MICROPROCESSEUR DOTE D'UN TEL DISPOSITIF
    7.
    发明专利
    DISPOSITIF DE GENERATION DE SUIVI DE BRANCHEMENT POUR MICROPROCESSEUR ET MICROPROCESSEUR DOTE D'UN TEL DISPOSITIF 未知

    公开(公告)号：FR2882832A1

    公开(公告)日：2006-09-08

    申请号：FR0502187

    申请日：2005-03-04

    Applicant: ST MICROELECTRONICS SA

    Inventor： ALOFS THOMAS

    IPC: G06F9/30 ,  G06F11/36

    Abstract: 1. Dispositif de génération d'un suivi d'adresses de saut pour un microcontrôleur, un microprocesseur ou une unité de traitement d'information doté d'un régime d'instructions comportant au moins une instruction conditionnelle et au moins une instruction de type multi-cycle, ledit dispositif comportant :- des moyens pour recevoir un premier signal (VALID) caractéristique d'une instruction réellement exécutée ;- des moyens pour recevoir un second signal (EXP) caractéristique d'une instruction de type multi-cycle ;- des moyens pour recevoir un troisième signal (DISC) caractéristique d'un saut de discontinuité entre une adresse de source et une adresse de destination d'un programme exécuté dans ledit microcontrôleur, microprocesseur ou ladite unité de traitement.- des moyens de stockage des adresses consécutives présentées par le pointeur d'adresses (10, 20, 30) ;- des moyens de traitement (50) desdits premier, second et troisième signal de manière à déterminer, le cas échéant, un couple formé d'une adresse de source et d'une adresse de destination pour un saut d'adresse ;- des moyens de stockage (40) dudit couple d'adresse.

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