公开(公告)号：DE69611325D1

公开(公告)日：2001-02-01

申请号：DE69611325

申请日：1996-06-17

Applicant: ST MICROELECTRONICS SA

Inventor： GUEDJ MARC ,  BRIGATI ALESSANDRO ,  AULAS MAXENCE ,  DEMANGE NICOLAS

IPC: G11C17/00 ,  G11C16/06 ,  H03K17/693 ,  H03K19/00

Abstract: A first input terminal receives a positive voltage (HPV) and a second input terminal (3) receives a negative input voltage (HVN). A first control logic signal (CS1) is applied to the pair of transistors (9, 10) to select the voltage at the output (4). A third input terminal (32) may be added to receive a second positive voltage (VP) which is connected to the output via a third transistor (31). A second control logic signal (CS2) is applied to an input terminal (33) and together with the first control signal by means of the control circuits (11, 13, 14, 15, 16, 30, 34) determines the voltage applied to the gates of the transistors (9, 10, 31) so as to select one of the inputs to present at the output.

公开(公告)号：DE69611325T2

公开(公告)日：2001-05-23

申请号：DE69611325

申请日：1996-06-17

Applicant: ST MICROELECTRONICS SA

Inventor： GUEDJ MARC ,  BRIGATI ALESSANDRO ,  AULAS MAXENCE ,  DEMANGE NICOLAS

IPC: G11C17/00 ,  G11C16/06 ,  H03K17/693 ,  H03K19/00

Abstract: A first input terminal receives a positive voltage (HPV) and a second input terminal (3) receives a negative input voltage (HVN). A first control logic signal (CS1) is applied to the pair of transistors (9, 10) to select the voltage at the output (4). A third input terminal (32) may be added to receive a second positive voltage (VP) which is connected to the output via a third transistor (31). A second control logic signal (CS2) is applied to an input terminal (33) and together with the first control signal by means of the control circuits (11, 13, 14, 15, 16, 30, 34) determines the voltage applied to the gates of the transistors (9, 10, 31) so as to select one of the inputs to present at the output.