公开(公告)号：DE602005019833D1

公开(公告)日：2010-04-22

申请号：DE602005019833

申请日：2005-11-30

Applicant: ST MICROELECTRONICS SA

Inventor： DEMANGE NICOLAS

IPC: G11C29/02

公开(公告)号：FR2889349A1

公开(公告)日：2007-02-02

申请号：FR0507912

申请日：2005-07-26

Applicant: ST MICROELECTRONICS SA

Inventor： LISART MATHIEU ,  DEMANGE NICOLAS

IPC: G11C7/06 ,  G06F12/14 ,  G06K19/07

Abstract: L'invention concerne un procédé de traitement de signaux électriques (ISO-ISm) parallèles, au moyen de circuits de traitement parallèles (CT0-CTm), comprenant des cycles successifs de traitement des signaux électriques selon une règle d'assignation des signaux électriques aux circuits de traitement. Selon l'invention, le procédé comprend, entre les cycles de traitement, une étape de modification de la règle d'assignation des signaux électriques (IS0-ISm) aux circuits de traitement (CT0-CTm), de sorte qu'un circuit de traitement traite des signaux électriques de rangs différents au cours de cycles de traitement différents. Application notamment à la sécurisation d'une mémoire pendant des phases de lecture de la mémoire et d'un circuit intégré à microprocesseur utilisant une telle mémoire.

公开(公告)号：DE69611325D1

公开(公告)日：2001-02-01

申请号：DE69611325

申请日：1996-06-17

Applicant: ST MICROELECTRONICS SA

Inventor： GUEDJ MARC ,  BRIGATI ALESSANDRO ,  AULAS MAXENCE ,  DEMANGE NICOLAS

IPC: G11C17/00 ,  G11C16/06 ,  H03K17/693 ,  H03K19/00

Abstract: A first input terminal receives a positive voltage (HPV) and a second input terminal (3) receives a negative input voltage (HVN). A first control logic signal (CS1) is applied to the pair of transistors (9, 10) to select the voltage at the output (4). A third input terminal (32) may be added to receive a second positive voltage (VP) which is connected to the output via a third transistor (31). A second control logic signal (CS2) is applied to an input terminal (33) and together with the first control signal by means of the control circuits (11, 13, 14, 15, 16, 30, 34) determines the voltage applied to the gates of the transistors (9, 10, 31) so as to select one of the inputs to present at the output.

公开(公告)号：FR2878644A1

公开(公告)日：2006-06-02

申请号：FR0412705

申请日：2004-11-30

Applicant: ST MICROELECTRONICS SA

Inventor： DEMANGE NICOLAS

IPC: G11C16/08 ,  G11C29/02

Abstract: L'invention porte sur une mémoire non volatile comprenant :-des lignes de mot donnant accès à des cellules mémoire;-un décodeur de lignes de mot (10) appliquant un signal d'activation correspondant à une adresse d'entrée sur une ligne de mot (WL) ;-un convertisseur (7) reproduisant sur des sorties (WL_LV) le signal d'activation en abaissant son niveau de tension ;-un circuit d'encodage (8) comprenant des transistors (81) à seuil de commutation inférieur au niveau de tension des sorties et connectés pour générer une adresse de sortie (Aout ) spécifique à une ligne de mot activée si cette ligne de mot est la seule activée ;-un circuit de test (9) générant un signal d'erreur si l'adresse d'entrée diffère de l'adresse de sortie.L'invention permet notamment de réduire la surface de silicium occupée par un circuit de test.

公开(公告)号：DE602006012765D1

公开(公告)日：2010-04-22

申请号：DE602006012765

申请日：2006-07-12

Applicant: ST MICROELECTRONICS SA

Inventor： LISART MATHIEU ,  DEMANGE NICOLAS

IPC: G11C7/24 ,  G11C7/10

Abstract: The method involves applying electrical signals (IS0 - ISm) each representing a state of one of selected memory cells to memory cell read circuits supplying a binary output signal representing state of the cell to which it is linked. A rule to allocate the signals to the circuits is modified by applying a permutation to a part of the signals, so that each read circuit processes electrical signals of different ranks during different reading cycles. The rule is randomly or pseudo-randomly modified for every T reading cycles, where T is a constant or a variable integer greater than or equal to 1. An independent claim is also included for a memory comprising memory cells.

公开(公告)号：DE602004003465D1

公开(公告)日：2007-01-11

申请号：DE602004003465

申请日：2004-02-19

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS SRL

Inventor： DEMANGE NICOLAS ,  CONTE ANTONINO ,  PRECISO SALVATORE ,  SIGNORELLO ALFREDO

IPC: G11C7/14 ,  G01N27/00 ,  G11C7/06 ,  G11C7/10 ,  G11C16/28

Abstract: A sensing circuit (120) for sensing currents, including at least one sense amplifier (122), comprising: a measure circuit branch (132i), having a measure node for receiving an input current (Ic) to be sensed, for converting the input current into a corresponding input voltage (V-); at least one comparison circuit branch (132o), having a comparison node for receiving a comparison current (Igs), for converting the comparison current into a corresponding comparison voltage (V+); and at least one voltage comparator (140) for comparing the input and comparison voltages, and means (N3s,135; N3s,135';N3s,135" ) for generating the comparison current based on a reference current (Ir), said means comprising: at least one voltage generator (135;135';135'') for receiving the reference current and for generating a corresponding sense amplifier biasing voltage (Vsab); and means (N3s) for converting the sense amplifier biasing voltage into the comparison current. The at least one voltage generator includes a first circuit branch (232i), having a first node for receiving the reference current, for converting the reference current into a corresponding reference voltage (Vref), a second circuit branch (232o), having a second node for receiving a regulation current (Ii), in current mirror configuration with the first circuit branch for mirroring a current (Img) corresponding to the reference current, the second circuit branch generating by conversion a non-regulated voltage (Vgen) corresponding to the mirrored current and to the regulation current, and voltage regulator means (N3g,240) receiving the reference voltage and the non-regulated voltage for regulating the sense amplifier biasing voltage by controlling the non-regulated voltage through the regulation current.

公开(公告)号：DE69611325T2

公开(公告)日：2001-05-23

申请号：DE69611325

申请日：1996-06-17

Applicant: ST MICROELECTRONICS SA

Inventor： GUEDJ MARC ,  BRIGATI ALESSANDRO ,  AULAS MAXENCE ,  DEMANGE NICOLAS

IPC: G11C17/00 ,  G11C16/06 ,  H03K17/693 ,  H03K19/00

Abstract: A first input terminal receives a positive voltage (HPV) and a second input terminal (3) receives a negative input voltage (HVN). A first control logic signal (CS1) is applied to the pair of transistors (9, 10) to select the voltage at the output (4). A third input terminal (32) may be added to receive a second positive voltage (VP) which is connected to the output via a third transistor (31). A second control logic signal (CS2) is applied to an input terminal (33) and together with the first control signal by means of the control circuits (11, 13, 14, 15, 16, 30, 34) determines the voltage applied to the gates of the transistors (9, 10, 31) so as to select one of the inputs to present at the output.