公开(公告)号：FR2786910A1

公开(公告)日：2000-06-09

申请号：FR9815461

申请日：1998-12-04

Applicant: ST MICROELECTRONICS SA

Inventor： GUEDJ MARC

IPC: G11C11/56

Abstract: The proposed memory circuit and the reading procedure are based on the utilization of the polarization voltage (VP) on the transistor gate equal to the voltage necessary to obtain a predetermined reference current (Iref) in the selected memory transistor (10) by comparing the current (Icell) in the transistor channel to the reference current (Iref). The decoding or reading of the memory stored data is carried out by decoding the polarization voltage (VP), by means of a decoder (CL) with output of high-value and low-value bits (MSb,LSb). The proposed memory cell comprises the current comparator (11), the polarization voltage generator (12) with output connected to the gate of transistor (10) of type e.g. MOS (metal-oxide-semiconductor) and the decoder (CL). The polarization voltage generator (12) is with inputs for the selection signal (LS) and the binary information of the current comparison. The integrated memory circuit comprises a set of bit lines, a set of word lines, and a set of transistors with floating gates placed at intersections of the word lines and the bit lines. Each transistor with floating gate is for the memory of an electric state representing a stored data. The integrated memory circuit further comprises at least one comparator (11) for comparing the current (Icell) in the selected bit line to the reference current (Iref), a voltage generator (12) with output of the polarization voltage (VP) increasing until the current in the bit line is lower than the reference current, and a decoder (CL). The integrated memory circuit for e.g. 2-bit or 4-bit words, comprises loading transistors connected to the bit lines, and the transistor gates connected to an address decoder. The integrated memory circuit organized for higher bit value words comprises a set of matrices, each containing the bit and the word lines and the floating gate memory transistors, utilizing the same row decoder. At the time of reading only the bit line read is under voltage.

公开(公告)号：DE69611325T2

公开(公告)日：2001-05-23

申请号：DE69611325

申请日：1996-06-17

Applicant: ST MICROELECTRONICS SA

Inventor： GUEDJ MARC ,  BRIGATI ALESSANDRO ,  AULAS MAXENCE ,  DEMANGE NICOLAS

IPC: G11C17/00 ,  G11C16/06 ,  H03K17/693 ,  H03K19/00

Abstract: A first input terminal receives a positive voltage (HPV) and a second input terminal (3) receives a negative input voltage (HVN). A first control logic signal (CS1) is applied to the pair of transistors (9, 10) to select the voltage at the output (4). A third input terminal (32) may be added to receive a second positive voltage (VP) which is connected to the output via a third transistor (31). A second control logic signal (CS2) is applied to an input terminal (33) and together with the first control signal by means of the control circuits (11, 13, 14, 15, 16, 30, 34) determines the voltage applied to the gates of the transistors (9, 10, 31) so as to select one of the inputs to present at the output.

公开(公告)号：FR2786910B1

公开(公告)日：2002-11-29

申请号：FR9815461

申请日：1998-12-04

Applicant: ST MICROELECTRONICS SA

Inventor： GUEDJ MARC

IPC: G11C11/56

Abstract: A circuit and method for reading a multiple-level floating-gate memory is provided. The reading is done by a gate bias voltage VP that is equal to the voltage needed to obtain a predetermined reference current Iref in the selected storage transistor. The decoding of the stored data element is done by the decoding of the bias voltage VP. Thus the circuit and method reduces the current flowing through the transistors during the reading and reduces the mean electrical stress undergone during each read operation.

公开(公告)号：DE69611325D1

公开(公告)日：2001-02-01

申请号：DE69611325

申请日：1996-06-17

Applicant: ST MICROELECTRONICS SA

Inventor： GUEDJ MARC ,  BRIGATI ALESSANDRO ,  AULAS MAXENCE ,  DEMANGE NICOLAS

IPC: G11C17/00 ,  G11C16/06 ,  H03K17/693 ,  H03K19/00

Abstract: A first input terminal receives a positive voltage (HPV) and a second input terminal (3) receives a negative input voltage (HVN). A first control logic signal (CS1) is applied to the pair of transistors (9, 10) to select the voltage at the output (4). A third input terminal (32) may be added to receive a second positive voltage (VP) which is connected to the output via a third transistor (31). A second control logic signal (CS2) is applied to an input terminal (33) and together with the first control signal by means of the control circuits (11, 13, 14, 15, 16, 30, 34) determines the voltage applied to the gates of the transistors (9, 10, 31) so as to select one of the inputs to present at the output.