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    1.
    发明专利
    未知

    公开(公告)号：FR2849260B1

    公开(公告)日：2005-03-11

    申请号：FR0216558

    申请日：2002-12-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  VINCENT EMMANUEL ,  BRUYERE SYLVIE ,  CANDELIER PHILIPPE ,  JACQUET FRANCOIS

    IPC: G11C14/00 ,  G11C17/14 ,  G11C11/412 ,  G11C11/417

    Abstract: The memory cell (10) comprises two inverter circuits (14,16) interconnected between the data nodes (N1,N2) so to form a memory circuit (12), two programming transistors (28,30) for implementing an irreversible degradation of the gate oxide layers of transistors (18,18'), and two transistors (32,34) for implementing the functioning of the memory cell after programming. Each inverter circuit (14,16) comprises supplementary MOS transistors (18,20;18',20') connected in series between a supply voltage source (VDD) and the ground circuit (22). Each inverter circuit comprises a p-MOS transistor (18,18') and an n-MOS transistor (20,20'), and the data nodes (N1,N2) are formed between the two transistors, n-MOS and p-MOS. The degraded MOS transistor is a transistor with thin gate oxide layer (GO1). The oxide layer is degraded at least locally so to obtain a variation of current through the transistor at the time of reading the cell. The programming transistors (28,30), or the diodes, are connected between the programming control line (PROG) and the transistors of the inverter circuits. The n-MOS programming transistors (28,30) ensure a selective connection of the gates of the transistors (18,18') to a programming voltage (VREF) at a level sufficient to cause the degradation of the gate oxide layers of the transistors. The inverter circuits are interconnected by the intermediary of a n-MOS transistor (32,34) connected to the control line (SRAM) of functioning the cell as the SRAM cell. The drain and the source electrodes of the transistors (32,34) are connected to the gates of the transistors of the inverter circuits.

    2.
    发明专利
    未知

    公开(公告)号：DE60301119T2

    公开(公告)日：2006-06-01

    申请号：DE60301119

    申请日：2003-12-08

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  VINCENT EMMANUEL ,  BRUYERE SYLVIE ,  CANDELIER PHILIPPE ,  JACQUET FRANCOIS

    IPC: G11C17/14 ,  G11C14/00

    Abstract: The memory cell (10) comprises two inverter circuits (14,16) interconnected between the data nodes (N1,N2) so to form a memory circuit (12), two programming transistors (28,30) for implementing an irreversible degradation of the gate oxide layers of transistors (18,18'), and two transistors (32,34) for implementing the functioning of the memory cell after programming. Each inverter circuit (14,16) comprises supplementary MOS transistors (18,20;18',20') connected in series between a supply voltage source (VDD) and the ground circuit (22). Each inverter circuit comprises a p-MOS transistor (18,18') and an n-MOS transistor (20,20'), and the data nodes (N1,N2) are formed between the two transistors, n-MOS and p-MOS. The degraded MOS transistor is a transistor with thin gate oxide layer (GO1). The oxide layer is degraded at least locally so to obtain a variation of current through the transistor at the time of reading the cell. The programming transistors (28,30), or the diodes, are connected between the programming control line (PROG) and the transistors of the inverter circuits. The n-MOS programming transistors (28,30) ensure a selective connection of the gates of the transistors (18,18') to a programming voltage (VREF) at a level sufficient to cause the degradation of the gate oxide layers of the transistors. The inverter circuits are interconnected by the intermediary of a n-MOS transistor (32,34) connected to the control line (SRAM) of functioning the cell as the SRAM cell. The drain and the source electrodes of the transistors (32,34) are connected to the gates of the transistors of the inverter circuits.

    Memory cell which is electrically programmable by degrading at least locally the gate oxide layer of a MOS transistor so to obtain a current variation in reading operation
    3.
    发明专利
    Memory cell which is electrically programmable by degrading at least locally the gate oxide layer of a MOS transistor so to obtain a current variation in reading operation 未知

    公开(公告)号：FR2846464A1

    公开(公告)日：2004-04-30

    申请号：FR0213497

    申请日：2002-10-29

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  VINCENT EMMANUEL ,  BRUYERE SYLVIE

    IPC: G11C11/56 ,  G11C17/14 ,  G11C17/08 ,  G11C17/18 ,  H01L27/115

    Abstract: The memory cell or point memory which is of electrically programmable read-only type comprises a MOS transistor with the gate oxide layer (14) and the gate (G) which is electrically connected. In programming operation the gate oxide layer (14) is degraded at least locally at point Z so to obtain in the reading operations a variation of current (Id) delivered by the transistor. The MOS transistor is a transistor with thin gate oxide layer (GO1), whose thickness is substantially equal to 2.5 nm. The gate oxide layer (14) is degraded as a function of used programming voltages. The degradation of the gate oxide layer is implemented in the full length of transistor channel (12), or in the vicinity of at least one electrode, source (S) and drain (D), in particular the drain electrode. A method (claimed) for programming the memory cell (claimed) consists of applying the programming voltages to the transistor electrodes which cause an irreversible degradation of the gate oxide layer of the transistor so that the read current (Id) is varied. In the course of programming the gate voltage is equal to at least 1.2 V, the voltage between the source and the drain is equal to about 3 V, and the bulk voltage is negative and qual to about -1 V. A method (claimed) for reading the memory cell consists of applying between the drain and the source a voltage in the range from 0.1 V to 1.2 V. An integrated circuit (claimed) comprises a central part with MOS transistors having the thin gate oxide layer (GO1) and a peripheral part with MOS transistors having a thicker gate oxide layer (GO2). The central part comprises a flat memory comprising memory cells with the MOS transistors having the thin gate oxide layer. In the write operation the programming voltages are applied to cause the degradation of the gate oxide layer of the selected transistor. A higher programming voltage is applied either to the drain or to the source of the memory cell so to cause degradations in the respective zones of the gate oxide layer. Each memory cell is also associated with another transistor allowing an adjustment of the source voltage of non-selected transistors. The thickness of the thicker gate oxide layer is substantially equal to 7 nm. The lower and the higher supply voltages are about 1.2 V and 3.3 V, respectively.

    4.
    发明专利
    未知

    公开(公告)号：FR2917231B1

    公开(公告)日：2009-10-02

    申请号：FR0755553

    申请日：2007-06-07

    Applicant: ST MICROELECTRONICS SA

    Inventor： CREMER SEBASTIEN ,  DELPECH PHILIPPE ,  BRUYERE SYLVIE

    IPC: H01L21/02 ,  H01L27/06

    Abstract: The method involves realizing components and superposed interconnections metallic level (M5) on a substrate (100), and realizing an insulating layer (104) formed above the interconnections metallic level. A horizontal metallic zone e.g. metallic band (108), of the interconnection metallic level is formed such that isolating blocks e.g. isolating pins (106), resulting from the insulating layer are incorporated in the metallic zones, where the metallic zone forms an lower reinforcement part of a metal insulation metal condenser/capacitor. An independent claim is also included for microelectronic device.

    5.
    发明专利
    未知

    公开(公告)号：DE60301119D1

    公开(公告)日：2005-09-01

    申请号：DE60301119

    申请日：2003-12-08

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  VINCENT EMMANUEL ,  BRUYERE SYLVIE ,  CANDELIER PHILIPPE ,  JACQUET FRANCOIS

    IPC: G11C14/00 ,  G11C17/14

    Abstract: The memory cell (10) comprises two inverter circuits (14,16) interconnected between the data nodes (N1,N2) so to form a memory circuit (12), two programming transistors (28,30) for implementing an irreversible degradation of the gate oxide layers of transistors (18,18'), and two transistors (32,34) for implementing the functioning of the memory cell after programming. Each inverter circuit (14,16) comprises supplementary MOS transistors (18,20;18',20') connected in series between a supply voltage source (VDD) and the ground circuit (22). Each inverter circuit comprises a p-MOS transistor (18,18') and an n-MOS transistor (20,20'), and the data nodes (N1,N2) are formed between the two transistors, n-MOS and p-MOS. The degraded MOS transistor is a transistor with thin gate oxide layer (GO1). The oxide layer is degraded at least locally so to obtain a variation of current through the transistor at the time of reading the cell. The programming transistors (28,30), or the diodes, are connected between the programming control line (PROG) and the transistors of the inverter circuits. The n-MOS programming transistors (28,30) ensure a selective connection of the gates of the transistors (18,18') to a programming voltage (VREF) at a level sufficient to cause the degradation of the gate oxide layers of the transistors. The inverter circuits are interconnected by the intermediary of a n-MOS transistor (32,34) connected to the control line (SRAM) of functioning the cell as the SRAM cell. The drain and the source electrodes of the transistors (32,34) are connected to the gates of the transistors of the inverter circuits.

    Memory cell of type permanent static random-access memory (SRAM), comprises two interconnected inverter circuits and transistors for programming by degradation of gate oxide layers
    7.
    发明专利
    Memory cell of type permanent static random-access memory (SRAM), comprises two interconnected inverter circuits and transistors for programming by degradation of gate oxide layers 未知

    公开(公告)号：FR2849260A1

    公开(公告)日：2004-06-25

    申请号：FR0216558

    申请日：2002-12-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  VINCENT EMMANUEL ,  BRUYERE SYLVIE ,  CANDELIER PHILIPPE ,  JACQUET FRANCOIS

    IPC: G11C14/00 ,  G11C17/14 ,  G11C11/412 ,  G11C11/417

    Abstract: The memory cell (10) comprises two inverter circuits (14,16) interconnected between the data nodes (N1,N2) so to form a memory circuit (12), two programming transistors (28,30) for implementing an irreversible degradation of the gate oxide layers of transistors (18,18'), and two transistors (32,34) for implementing the functioning of the memory cell after programming. Each inverter circuit (14,16) comprises supplementary MOS transistors (18,20;18',20') connected in series between a supply voltage source (VDD) and the ground circuit (22). Each inverter circuit comprises a p-MOS transistor (18,18') and an n-MOS transistor (20,20'), and the data nodes (N1,N2) are formed between the two transistors, n-MOS and p-MOS. The degraded MOS transistor is a transistor with thin gate oxide layer (GO1). The oxide layer is degraded at least locally so to obtain a variation of current through the transistor at the time of reading the cell. The programming transistors (28,30), or the diodes, are connected between the programming control line (PROG) and the transistors of the inverter circuits. The n-MOS programming transistors (28,30) ensure a selective connection of the gates of the transistors (18,18') to a programming voltage (VREF) at a level sufficient to cause the degradation of the gate oxide layers of the transistors. The inverter circuits are interconnected by the intermediary of a n-MOS transistor (32,34) connected to the control line (SRAM) of functioning the cell as the SRAM cell. The drain and the source electrodes of the transistors (32,34) are connected to the gates of the transistors of the inverter circuits.

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