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    CIRCUIT INTEGRE PHOTONIQUE ET PROCEDE DE FABRICATION
    1.
    发明专利
    CIRCUIT INTEGRE PHOTONIQUE ET PROCEDE DE FABRICATION 未知

    公开(公告)号：FR3007589A1

    公开(公告)日：2014-12-26

    申请号：FR1355991

    申请日：2013-06-24

    Applicant: ST MICROELECTRONICS CROLLES 2 ,  ST MICROELECTRONICS SA

    Inventor： CHANTRE ALAIN ,  CREMER SEBASTIEN

    IPC: H01S5/026

    Abstract: Circuit intégré photonique, comprenant une couche de silicium contenant un guide d'ondes (GO) et au moins un autre composant photonique, une première région isolante (4) disposée au dessus d'une première face (F1) de la couche de silicium et encapsulant un ou plusieurs niveaux de métallisation (M1-M4), une deuxième région isolante (9) disposée au dessus d'une deuxième face (F2) de la couche de silicium et encapsulant au moins le milieu amplificateur (800) d'une source laser (SL) optiquement couplée avec le guide d'ondes (GO).

    4.
    发明专利
    未知

    公开(公告)号：DE60307174D1

    公开(公告)日：2006-09-14

    申请号：DE60307174

    申请日：2003-05-15

    Applicant: ST MICROELECTRONICS SA

    Inventor： DELPECH PHILIPPE ,  CREMER SEBASTIEN ,  MARTY MICHEL

    IPC: H01L21/02 ,  H01L23/522

    Abstract: Capacitor is manufactured in substrate (1) by digging recess into substrate; forming first conformal layer of insulating material; forming second conductive layer; forming third layer of conductive or insulating material filling up recess; digging trenches into third layer, across entire height; depositing fourth layer of conductive material; forming fifth layer of dielectric material; and depositing sixth layer of conductive material. An Independent claim is also included for a capacitor formed in a substrate comprising: (a) a recess (2) dug into a substrate; (b) a first layer of a dielectric material covering the walls, the bottom and the edges of the recess; (c) a second layer of a conductive material covering the first layer; (d) a third layer of a conductive or insulating material filling the recess; (e) trenches crossing the third layer; (f) a fourth layer of a conductive material covering the walls, the bottoms as well as the intervals between these trenches and the edges; (g) a fifth layer of a dielectric material covering the fourth layer; and (h) a sixth layer of a conductive material covering the fifth layer.

    9.
    发明专利
    未知

    公开(公告)号：FR2917231B1

    公开(公告)日：2009-10-02

    申请号：FR0755553

    申请日：2007-06-07

    Applicant: ST MICROELECTRONICS SA

    Inventor： CREMER SEBASTIEN ,  DELPECH PHILIPPE ,  BRUYERE SYLVIE

    IPC: H01L21/02 ,  H01L27/06

    Abstract: The method involves realizing components and superposed interconnections metallic level (M5) on a substrate (100), and realizing an insulating layer (104) formed above the interconnections metallic level. A horizontal metallic zone e.g. metallic band (108), of the interconnection metallic level is formed such that isolating blocks e.g. isolating pins (106), resulting from the insulating layer are incorporated in the metallic zones, where the metallic zone forms an lower reinforcement part of a metal insulation metal condenser/capacitor. An independent claim is also included for microelectronic device.

    10.
    发明专利
    未知

    公开(公告)号：FR2839811A1

    公开(公告)日：2003-11-21

    申请号：FR0205965

    申请日：2002-05-15

    Applicant: ST MICROELECTRONICS SA

    Inventor： DELPECH PHILIPPE ,  CREMER SEBASTIEN ,  MARTY MICHEL

    IPC: H01L21/02 ,  H01L23/522 ,  H01L21/334 ,  H01L29/94

    Abstract: Capacitor is manufactured in substrate (1) by digging recess into substrate; forming first conformal layer of insulating material; forming second conductive layer; forming third layer of conductive or insulating material filling up recess; digging trenches into third layer, across entire height; depositing fourth layer of conductive material; forming fifth layer of dielectric material; and depositing sixth layer of conductive material. An Independent claim is also included for a capacitor formed in a substrate comprising: (a) a recess (2) dug into a substrate; (b) a first layer of a dielectric material covering the walls, the bottom and the edges of the recess; (c) a second layer of a conductive material covering the first layer; (d) a third layer of a conductive or insulating material filling the recess; (e) trenches crossing the third layer; (f) a fourth layer of a conductive material covering the walls, the bottoms as well as the intervals between these trenches and the edges; (g) a fifth layer of a dielectric material covering the fourth layer; and (h) a sixth layer of a conductive material covering the fifth layer.

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