中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

29 records (took 0.024 seconds)

    MOS transistor with extended drain region has spacer on the drain side extending from side of gate to drain region and entirely covering the drain extension region
    5.
    发明专利
    MOS transistor with extended drain region has spacer on the drain side extending from side of gate to drain region and entirely covering the drain extension region 未知

    公开(公告)号：FR2801421A1

    公开(公告)日：2001-05-25

    申请号：FR9914484

    申请日：1999-11-18

    Applicant: ST MICROELECTRONICS SA

    Inventor： DELPECH PHILIPPE ,  COTTIN DIDIER

    IPC: H01L21/336 ,  H01L29/78

    Abstract: MOS transistor (40) comprises gate (20) formed on Si substrate (21), drain (23) and source (24) regions and their extension regions extending to transistor channel (19), and spacers (25, 28) isolating gate sides from drain and source regions. Drain region is further away from the gate than the source region, and drain extension region (LDD1) is more extended than source extension region (LDD2). The spacer (25) on the drain side extends from the side of the gate to the drain (23) region and entirely covers the drain extension region (LDD1) An Independent claim is given for a method used for production of the above MOS transistor. Production of the MOS transistor involves forming a gate (20) on a silicon substrate (21) and implantation of drain (23) and source (24) extension regions on both sides of the gate (20). Disymmetric isolating spacers (25, 28) are formed on the sides of the gate (2) in a process that includes: (i) forming spacers of the same length by deposition and etching of a first insulating layer; (ii) extending the spacers by deposition and etching of a second insulating layer; and (iii) removing the second insulating layer on the source side spacer without removing the second insulating layer from the spacer on the drain side.

    6.
    发明专利
    未知

    公开(公告)号：FR2917231B1

    公开(公告)日：2009-10-02

    申请号：FR0755553

    申请日：2007-06-07

    Applicant: ST MICROELECTRONICS SA

    Inventor： CREMER SEBASTIEN ,  DELPECH PHILIPPE ,  BRUYERE SYLVIE

    IPC: H01L21/02 ,  H01L27/06

    Abstract: The method involves realizing components and superposed interconnections metallic level (M5) on a substrate (100), and realizing an insulating layer (104) formed above the interconnections metallic level. A horizontal metallic zone e.g. metallic band (108), of the interconnection metallic level is formed such that isolating blocks e.g. isolating pins (106), resulting from the insulating layer are incorporated in the metallic zones, where the metallic zone forms an lower reinforcement part of a metal insulation metal condenser/capacitor. An independent claim is also included for microelectronic device.

    7.
    发明专利
    未知

    公开(公告)号：FR2839811A1

    公开(公告)日：2003-11-21

    申请号：FR0205965

    申请日：2002-05-15

    Applicant: ST MICROELECTRONICS SA

    Inventor： DELPECH PHILIPPE ,  CREMER SEBASTIEN ,  MARTY MICHEL

    IPC: H01L21/02 ,  H01L23/522 ,  H01L21/334 ,  H01L29/94

    Abstract: Capacitor is manufactured in substrate (1) by digging recess into substrate; forming first conformal layer of insulating material; forming second conductive layer; forming third layer of conductive or insulating material filling up recess; digging trenches into third layer, across entire height; depositing fourth layer of conductive material; forming fifth layer of dielectric material; and depositing sixth layer of conductive material. An Independent claim is also included for a capacitor formed in a substrate comprising: (a) a recess (2) dug into a substrate; (b) a first layer of a dielectric material covering the walls, the bottom and the edges of the recess; (c) a second layer of a conductive material covering the first layer; (d) a third layer of a conductive or insulating material filling the recess; (e) trenches crossing the third layer; (f) a fourth layer of a conductive material covering the walls, the bottoms as well as the intervals between these trenches and the edges; (g) a fifth layer of a dielectric material covering the fourth layer; and (h) a sixth layer of a conductive material covering the fifth layer.

    8.
    发明专利
    未知

    公开(公告)号：FR2801426B1

    公开(公告)日：2002-10-11

    申请号：FR9914486

    申请日：1999-11-18

    Applicant: ST MICROELECTRONICS SA

    Inventor： DELPECH PHILIPPE ,  ARNAL VINCENT ,  LIS SANDRA

    IPC: H01L21/02 ,  H01L21/314 ,  H01L29/92 ,  H01G4/08 ,  H01G4/33

    Abstract: An integrated circuit capacitor includes a substrate, a first metal electrode on the substrate, and a dielectric layer on the first metal electrode. The dielectric layer includes a homogeneous combination of at least two dielectric materials having permittivities varying in an opposite way based upon an electric field, with a proportion of each dielectric material being chosen so that the integrated circuit capacitor has a desired voltage linearity. A second metal electrode is on the dielectric layer.

    10.
    发明专利
    未知

    公开(公告)号：FR2783093A1

    公开(公告)日：2000-03-10

    申请号：FR9811221

    申请日：1998-09-04

    Applicant: ST MICROELECTRONICS SA

    Inventor： DELPECH PHILIPPE ,  ROBILLIART ETIENNE ,  DUTARTRE DIDIER

    IPC: H01L21/02 ,  H01L29/92

    Abstract: Built-in capacitance (C1) on a silicon substrate (7) comprises a first highly doped polysilicon electrode (1), a thin layer (3) of silicon oxide, a second polysilicon electrode (10) and a silicide layer (4) over the second electrode. The second electrode has a high dopant concentration at the interface with the silicon oxide and a relatively low dopant concentration at the interface with the silicide layer. An Independent claim is also included for an integrated circuit, comprising at least one capacitance as above.

Patent Agency Ranking