公开(公告)号：FR2857150A1

公开(公告)日：2005-01-07

申请号：FR0307960

申请日：2003-07-01

Applicant: ST MICROELECTRONICS SA

Inventor： JACQUET FRANCOIS ,  CANDELLIER PHILIPPE ,  CERUTTI ROBIN ,  CORONEL PHILIPPE ,  MAZOYER PASCALE

IPC: G11C11/405 ,  H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  G11C11/401 ,  H01L21/8242

Abstract: The unit has a pair of cells (C1, C2) for storing two independent bits and including field effect transistors with grid (4, 14), respectively. A channel is arranged in a source zone (102), and the two transistors are arranged in between the source zone and a drain zone. An electrode of single polarization (24) is arranged between intermediate portions (1, 11) of the two transistors. An independent claim is also included for a method for manufacturing an integrated DRAM on a surface of a substrate.