公开(公告)号：JP2006121082A

公开(公告)日：2006-05-11

申请号：JP2005302800

申请日：2005-10-18

Applicant: St Microelectronics Sa ,  Stmicroelectronics (Crolles 2) Sas ,  エスティマイクロエレクトロニクス エスエー ,  エスティマイクロエレクトロニクス(クロル 2)エスエーエスSTMicroelectronics (Crolles 2)SAS

Inventor： LENOBLE DAMIEN ,  CORONEL PHILIPPE ,  CERUTTI ROBIN

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L21/76805 ,  H01L21/26506 ,  H01L21/28061 ,  H01L21/76814 ,  H01L23/485 ,  H01L29/66545 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an easy method for forming a compact pad whose manufacturing cost can be reduced.
SOLUTION: A region 51 is an area 510 that extends at least up to part of the front surface of the region, and can be locally changed for the purpose of forming the area using a material that can be selectively removed from the region. This region is covered with an insulating material 7, and an orifice 90 that appears on the front surface of the area 510 is formed in the insulating material. The material that can be selectively removed is removed from this area through the orifice so that a cavity 520 may be formed in place of this area. The cavity and the orifice are filled up with at least one conductive material 91.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于形成其制造成本可以降低的紧凑型垫的简单方法。 解决方案：区域51是至少延伸到区域的前表面的一部分的区域510，并且可以局部地改变以便使用可以从区域中选择性地去除的材料形成区域 。 该区域被绝缘材料7覆盖，并且在绝缘材料中形成出现在区域510的前表面上的孔口90。 可以选择性地除去的材料通过孔口从该区域移除，从而可以形成空腔520来代替该区域。 空腔和孔口填充有至少一个导电材料91.版权所有（C）2006，JPO＆NCIPI

公开(公告)号：FR2853454B1

公开(公告)日：2005-07-15

申请号：FR0304143

申请日：2003-04-03

Applicant: ST MICROELECTRONICS SA

Inventor： CORONEL PHILIPPE ,  MORAND YVES ,  SKOTNICKI THOMAS ,  CERUTTI ROBIN

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

Abstract: A MOS transistor formed in a silicon substrate (101) comprises: (a) an active zone (100) surrounded by an insulating partition (102); (b) a first conducting strip (103) covering a central strip of the active zone; (c) one or more second conducting strips (105, 106, 107) placed in the active zone plumb with the first strip; (d) some conducting regions (108, 109) placed in two cavities in the insulating partition and joined to the ends of the first and second strips; (e) the surfaces of the silicon opposite the strips and conducting regions are covered with an insulator (130) constituting an oxide grid. An independent claim is also included for the production of this MOS transistor.

公开(公告)号：FR2857150A1

公开(公告)日：2005-01-07

申请号：FR0307960

申请日：2003-07-01

Applicant: ST MICROELECTRONICS SA

Inventor： JACQUET FRANCOIS ,  CANDELLIER PHILIPPE ,  CERUTTI ROBIN ,  CORONEL PHILIPPE ,  MAZOYER PASCALE

IPC: G11C11/405 ,  H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  G11C11/401 ,  H01L21/8242

Abstract: The unit has a pair of cells (C1, C2) for storing two independent bits and including field effect transistors with grid (4, 14), respectively. A channel is arranged in a source zone (102), and the two transistors are arranged in between the source zone and a drain zone. An electrode of single polarization (24) is arranged between intermediate portions (1, 11) of the two transistors. An independent claim is also included for a method for manufacturing an integrated DRAM on a surface of a substrate.

公开(公告)号：FR2853454A1

公开(公告)日：2004-10-08

申请号：FR0304143

申请日：2003-04-03

Applicant: ST MICROELECTRONICS SA

Inventor： CORONEL PHILIPPE ,  MORAND YVES ,  SKOTNICKI THOMAS ,  CERUTTI ROBIN

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

Abstract: A MOS transistor formed in a silicon substrate (101) comprises: (a) an active zone (100) surrounded by an insulating partition (102); (b) a first conducting strip (103) covering a central strip of the active zone; (c) one or more second conducting strips (105, 106, 107) placed in the active zone plumb with the first strip; (d) some conducting regions (108, 109) placed in two cavities in the insulating partition and joined to the ends of the first and second strips; (e) the surfaces of the silicon opposite the strips and conducting regions are covered with an insulator (130) constituting an oxide grid. An independent claim is also included for the production of this MOS transistor.