公开(公告)号：JP2001319889A

公开(公告)日：2001-11-16

申请号：JP2001097867

申请日：2001-03-30

Applicant: ST MICROELECTRONICS SA ,  KONINKL PHILIPS ELECTRONICS NV

Inventor： DE COSTER WALTER ,  LUNENBORG MEINDERT ,  INARD ALAIN ,  GUELEN JOS

IPC: H01L21/76 ,  H01L21/265 ,  H01L21/266 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L29/10 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide an MOS transistor having a voltage threshold causing no damage on the quality by avoiding troubles in conventional technology. SOLUTION: The method for forming an active area surrounded with an insulating area in a semiconductor substrate includes steps for forming in the substrate a trench surrounding the active area, filling the trench with an insulating material to form an edge extending beyond the substrate surface at the periphery of the active area, forming a spacer at the periphery of the edge, and implanting a dopant, whereby the implantation in the area located under the spacer is less deep than in the rest of the active area.

公开(公告)号：FR2844096A1

公开(公告)日：2004-03-05

申请号：FR0210779

申请日：2002-08-30

Applicant: ST MICROELECTRONICS SA ,  KONINKL PHILIPS ELECTRONICS NV

Inventor： KORDIC SRDJAN ,  INARD ALAIN ,  ROUSSEL CELINE ,  GAYET PHILIPPE

IPC: H01L21/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L23/522 ,  H01L27/08 ,  H01L21/302

Abstract: Fabrication of integrated circuit comprises formation and withdrawal of conducting inserts. Some components (10, 20) of electric circuit are incorporated in some insulating materials (2, 4) superposed above substrate (1). Exclusion volume is arranged around certain components (10) sensitive to electrostatic coupling whilst conferring flat surface (S2) to each material (2, 4) at end of polishing.

公开(公告)号：FR2792113B1

公开(公告)日：2002-08-09

申请号：FR9904269

申请日：1999-04-06

Applicant: ST MICROELECTRONICS SA

Inventor： DE COSTER WALTER ,  INARD ALAIN

IPC: H01L21/762 ,  H01L29/786

公开(公告)号：FR2873130A1

公开(公告)日：2006-01-20

申请号：FR0407982

申请日：2004-07-19

Applicant: ST MICROELECTRONICS SA

Inventor： PETITDIDIER SEBASTIEN ,  INARD ALAIN

IPC: C23G1/10 ,  C23G1/06 ,  H01L21/77

Abstract: L'invention porte sur un procédé de traitement des surfaces de cuivre pour l'élimination des résidus carbonés, obtenus lors d'un polissage mécano-chimique, comprenant une première étape de rinçage à l'eau suivi d'une seconde étape de rinçage chimique utilisant une solution comprenant un inhibiteur de corrosion et un acide organique.

公开(公告)号：FR2784797B1

公开(公告)日：2002-08-23

申请号：FR9812882

申请日：1998-10-14

Applicant: ST MICROELECTRONICS SA

Inventor： BOUTIN DANIEL ,  INARD ALAIN ,  BOLT MICHAEL ,  LUCE EMMANUELLE ,  BARLA KATHY

IPC: H01L23/544 ,  H01L21/77 ,  G03F7/23

公开(公告)号：FR2807206A1

公开(公告)日：2001-10-05

申请号：FR0004174

申请日：2000-03-31

Applicant: ST MICROELECTRONICS SA

Inventor： DE COSTER WALTER ,  LUNENBORG MEINDERT ,  INARD ALAIN ,  GUELEN JOS

IPC: H01L21/76 ,  H01L21/265 ,  H01L21/266 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L29/10 ,  H01L29/78 ,  H01L21/334

Abstract: A method of forming an active area surrounded with an insulating area in a semiconductor substrate, including the steps of forming in the substrate a trench surrounding an active area; filling the trench with an insulating material to form an edge extending beyond the substrate surface at the periphery of the active area; forming a spacer at the periphery of said edge; and implanting a dopant, whereby the implantation in the area located under the spacer is less deep than in the rest of the active area.

公开(公告)号：FR2784797A1

公开(公告)日：2000-04-21

申请号：FR9812882

申请日：1998-10-14

Applicant: ST MICROELECTRONICS SA

Inventor： BOUTIN DANIEL ,  INARD ALAIN ,  BOLT MICHAEL ,  LUCE EMMANUELLE ,  BARLA KATHY

IPC: H01L23/544 ,  H01L21/77 ,  G03F7/23

Abstract: An integrated circuit manufacturing process, comprises alignment mark zone etching, stop layer deposition, isolation trench etching, oxide layer deposition, oxide layer etching from the marking zone and chemical-mechanical polishing. An integrated circuit (IC) manufacturing process comprises: (a) etching a silicon substrate to form a marking zone (17) with alignment grooves for a photo-repeater; (b) depositing a stop layer on the substrate; (c) etching isolation trenches; (d) depositing a silicon oxide layer on the circuit and etching the layer from the marking zone; and (e) subjecting the IC structure to chemical-mechanical polishing.

公开(公告)号：FR2910715B1

公开(公告)日：2009-06-26

申请号：FR0655813

申请日：2006-12-21

Applicant: ST MICROELECTRONICS SA

Inventor： SANCHEZ YANNICK ,  HOTELLIER NICOLAS ,  INARD ALAIN

IPC: H01L31/18 ,  G02B3/00 ,  H01L27/146 ,  H01L31/0232

公开(公告)号：DE60136026D1

公开(公告)日：2008-11-20

申请号：DE60136026

申请日：2001-03-29

Applicant: NXP BV ,  ST MICROELECTRONICS SA

Inventor： DE COSTER WALTER ,  LUNENBORG MEINDERT ,  INARD ALAIN ,  GUELEN JOS

IPC: H01L21/76 ,  H01L29/10 ,  H01L21/265 ,  H01L21/266 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L29/78

Abstract: A method of forming an active area surrounded with an insulating area in a semiconductor substrate, including the steps of forming in the substrate a trench surrounding an active area; filling the trench with an insulating material to form an edge extending beyond the substrate surface at the periphery of the active area; forming a spacer at the periphery of said edge; and implanting a dopant, whereby the implantation in the area located under the spacer is less deep than in the rest of the active area.

公开(公告)号：FR2910715A1

公开(公告)日：2008-06-27

申请号：FR0655813

申请日：2006-12-21

Applicant: ST MICROELECTRONICS SA

Inventor： SANCHEZ YANNICK ,  HOTELLIER NICOLAS ,  INARD ALAIN

IPC: H01L31/18 ,  G02B3/00 ,  H01L27/146 ,  H01L31/0232

Abstract: Procédé et appareillage pour réaliser des micro-lentilles optiques (5) sur une couche antérieure (3) d'un dispositif semi-conducteur, dans lequel on dépose une ultime couche en un matériau adapté ; on réalise des rainures croisées dans ladite couche ultime, jusqu'à ladite couche antérieure, de façon à constituer des plots espacés ; et on effectue un traitement de façon à provoquer un ramollissement desdits plots générant un fluage de ces derniers leur conférant une forme bombée et on provoque leur durcissement, dans lesquels, pour effectuer ledit traitement, on place le dispositif semi-conducteur dans la chambre d'une enceinte, à une température basse ; et on fait fonctionner des moyens de chauffage de ladite chambre, des moyens pour générer un rayonnement ultra-violet vers lesdits plots et des moyens pour générer dans ladite chambre un plasma de façon que, lors dudit fluage et dudit durcissement, les bords voisins desdits plots ne fusionnent pas.Dispositif semi-conducteur à micro-lentilles optiques comprenant des moyens anti-fusion (7) de ces micro-lentilles.