公开(公告)号：JP2001319889A

公开(公告)日：2001-11-16

申请号：JP2001097867

申请日：2001-03-30

Applicant: ST MICROELECTRONICS SA ,  KONINKL PHILIPS ELECTRONICS NV

Inventor： DE COSTER WALTER ,  LUNENBORG MEINDERT ,  INARD ALAIN ,  GUELEN JOS

IPC: H01L21/76 ,  H01L21/265 ,  H01L21/266 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L29/10 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide an MOS transistor having a voltage threshold causing no damage on the quality by avoiding troubles in conventional technology. SOLUTION: The method for forming an active area surrounded with an insulating area in a semiconductor substrate includes steps for forming in the substrate a trench surrounding the active area, filling the trench with an insulating material to form an edge extending beyond the substrate surface at the periphery of the active area, forming a spacer at the periphery of the edge, and implanting a dopant, whereby the implantation in the area located under the spacer is less deep than in the rest of the active area.

公开(公告)号：FR2844096A1

公开(公告)日：2004-03-05

申请号：FR0210779

申请日：2002-08-30

Applicant: ST MICROELECTRONICS SA ,  KONINKL PHILIPS ELECTRONICS NV

Inventor： KORDIC SRDJAN ,  INARD ALAIN ,  ROUSSEL CELINE ,  GAYET PHILIPPE

IPC: H01L21/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L23/522 ,  H01L27/08 ,  H01L21/302

Abstract: Fabrication of integrated circuit comprises formation and withdrawal of conducting inserts. Some components (10, 20) of electric circuit are incorporated in some insulating materials (2, 4) superposed above substrate (1). Exclusion volume is arranged around certain components (10) sensitive to electrostatic coupling whilst conferring flat surface (S2) to each material (2, 4) at end of polishing.

公开(公告)号：JP2004165672A

公开(公告)日：2004-06-10

申请号：JP2003385102

申请日：2003-11-14

Applicant: Koninkl Philips Electronics Nv ,  Stmicroelectronics Sa ,  エステーミクロエレクトロニクス ソシエテ アノニム ,  コニンクリユケ フィリプス エレクトロニクス ナムローゼ フェンノートシャップKoninklijke Philips Electronics N.V.

Inventor： KORDIC SRDJAN ,  ROUSSEL CELINE ,  INARD ALAIN

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/768 ,  H01L21/76838 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To decrease possibility that voids are formed in an interface between a connector and an electric line. SOLUTION: Apparatus that electrically connects two conduction lines 1, 2 in an integrated circuit has a first conductive connector 3a between the two lines. The apparatus further has additional interfaces 3b to 3g or 6a to 6f for one of two lines, the faces being different from interfaces between the first connector and the lines, parallel to the direction along which electric current for the line flows, and different from a lateral interface between an insulating material and the line. The additional interfaces are disposed at a position in a substantially smaller distance than width of the line from the first connector 3a. The additional interfaces are obtained by disposing second electrically-conductive connectors 3b to 3g between the two lines 1, 2, or disposing ribs 6a to 6f on the line, or disposing cut on at least one of the faces of the line. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2001319969A

公开(公告)日：2001-11-16

申请号：JP2001081064

申请日：2001-03-21

Applicant: KONINKL PHILIPS ELECTRONICS NV

Inventor： INARD ALAIN ,  ZULIAN DOMINIQUE CECILE ,  LEVY DIDIER ,  LUNENBORG MEINDERT MARTIN ,  DE COSTER WALTER JAN AUGUST ,  OBERLIN JEAN-CLAUDE

IPC: H01L21/76 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/08 ,  H01L27/108 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming an insulation region in a periphery of an active region of a semiconductor substrate. SOLUTION: In a method for forming an insulation region (14) in a periphery of an active region (12) of a semiconductor substrate (10), this method contains the step that a trench is formed in a periphery of the active region (12) in the substrate, and the trench is filled up with a first material, and the insulation region (14) projecting from the surface of the substrate in the periphery of the active region is formed as a vertical projection in its margin. In the margin of the active region, an angle of the projection of the insulation region is gotten dull. A semiconductor device is formed by use of the above method.

公开(公告)号：FR2792113B1

公开(公告)日：2002-08-09

申请号：FR9904269

申请日：1999-04-06

Applicant: ST MICROELECTRONICS SA

Inventor： DE COSTER WALTER ,  INARD ALAIN

IPC: H01L21/762 ,  H01L29/786

公开(公告)号：FR2873130A1

公开(公告)日：2006-01-20

申请号：FR0407982

申请日：2004-07-19

Applicant: ST MICROELECTRONICS SA

Inventor： PETITDIDIER SEBASTIEN ,  INARD ALAIN

IPC: C23G1/10 ,  C23G1/06 ,  H01L21/77

Abstract: L'invention porte sur un procédé de traitement des surfaces de cuivre pour l'élimination des résidus carbonés, obtenus lors d'un polissage mécano-chimique, comprenant une première étape de rinçage à l'eau suivi d'une seconde étape de rinçage chimique utilisant une solution comprenant un inhibiteur de corrosion et un acide organique.

公开(公告)号：FR2784797B1

公开(公告)日：2002-08-23

申请号：FR9812882

申请日：1998-10-14

Applicant: ST MICROELECTRONICS SA

Inventor： BOUTIN DANIEL ,  INARD ALAIN ,  BOLT MICHAEL ,  LUCE EMMANUELLE ,  BARLA KATHY

IPC: H01L23/544 ,  H01L21/77 ,  G03F7/23

公开(公告)号：FR2807206A1

公开(公告)日：2001-10-05

申请号：FR0004174

申请日：2000-03-31

Applicant: ST MICROELECTRONICS SA

Inventor： DE COSTER WALTER ,  LUNENBORG MEINDERT ,  INARD ALAIN ,  GUELEN JOS

IPC: H01L21/76 ,  H01L21/265 ,  H01L21/266 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L29/10 ,  H01L29/78 ,  H01L21/334

Abstract: A method of forming an active area surrounded with an insulating area in a semiconductor substrate, including the steps of forming in the substrate a trench surrounding an active area; filling the trench with an insulating material to form an edge extending beyond the substrate surface at the periphery of the active area; forming a spacer at the periphery of said edge; and implanting a dopant, whereby the implantation in the area located under the spacer is less deep than in the rest of the active area.

公开(公告)号：FR2784797A1

公开(公告)日：2000-04-21

申请号：FR9812882

申请日：1998-10-14

Applicant: ST MICROELECTRONICS SA

Inventor： BOUTIN DANIEL ,  INARD ALAIN ,  BOLT MICHAEL ,  LUCE EMMANUELLE ,  BARLA KATHY

IPC: H01L23/544 ,  H01L21/77 ,  G03F7/23

Abstract: An integrated circuit manufacturing process, comprises alignment mark zone etching, stop layer deposition, isolation trench etching, oxide layer deposition, oxide layer etching from the marking zone and chemical-mechanical polishing. An integrated circuit (IC) manufacturing process comprises: (a) etching a silicon substrate to form a marking zone (17) with alignment grooves for a photo-repeater; (b) depositing a stop layer on the substrate; (c) etching isolation trenches; (d) depositing a silicon oxide layer on the circuit and etching the layer from the marking zone; and (e) subjecting the IC structure to chemical-mechanical polishing.

公开(公告)号：FR2910715B1

公开(公告)日：2009-06-26

申请号：FR0655813

申请日：2006-12-21

Applicant: ST MICROELECTRONICS SA

Inventor： SANCHEZ YANNICK ,  HOTELLIER NICOLAS ,  INARD ALAIN

IPC: H01L31/18 ,  G02B3/00 ,  H01L27/146 ,  H01L31/0232