公开(公告)号：WO0135448A2

公开(公告)日：2001-05-17

申请号：PCT/FR0003153

申请日：2000-11-10

Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM ,  SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  MALLARDEAU CATHERINE

Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  MALLARDEAU CATHERINE

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/60

Abstract: The invention concerns a method which consists in forming on a substrate (1) coated with a dielectric material layer (3) provided with a window (3a), a stack of successive layers alternately of germanium or SiGe alloy (4, 6, 8) and polycrystalline silicon (5, 7, 9); selective partial elimination of the germanium or SiGe alloy layers, to form an tree-like structure; forming a thin layer of dielectric material (10) on the tree-like structure; and coating the tree-like structure with polycrystalline silicon (11). The invention is useful for making dynamic random-access memories.

Abstract translation: 本发明涉及一种方法，该方法包括在涂覆有设置有窗口（3a）的介电材料层（3）的基底（1）上，交替地具有锗或SiGe合金（4,6,8）的叠层， 和多晶硅（5,7,9）; 选择性地部分消除锗或SiGe合金层，形成树状结构; 在树状结构上形成介电材料薄层（10）; 并用多晶硅（11）涂覆树状结构。 本发明对于制作动态随机存取存储器是有用的。

公开(公告)号：FR2806833B1

公开(公告)日：2002-06-14

申请号：FR0003844

申请日：2000-03-27

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  HAOND MICHEL

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/78

Abstract: A method for making a MOS transistor includes forming a first gate within a silicon-on-insulator substrate, forming a semiconductor channel region transversely surmounting the first gate, and forming semiconductor drain and source regions on each side of the channel region. The semiconductor channel region and drain and source regions may be produced by epitaxy on an upper surface of the first gate. The channel region may be isolated from the upper surface of the first gate by forming a tunnel under the channel region and at least partially filling the tunnel with a first dielectric. The second gate is formed on the channel region and transverse to the channel region. The second gate may be separated from an upper surface of the channel region by a second dielectric.

公开(公告)号：FR2801970A1

公开(公告)日：2001-06-08

申请号：FR9915410

申请日：1999-12-07

Applicant: ST MICROELECTRONICS SA

Inventor： JAOUEN HERVE ,  SKOTNICKI THOMAS ,  JURCZAK MALGORZATA

IPC: G01D5/242 ,  G01L9/00 ,  G10K9/13 ,  G01D5/241 ,  H01L43/12

Abstract: The invention concerns a magnetic sensor comprising a thin deformable membrane (3) made of conductive material forming a first armature of a capacitor and traversed by an electric current, a second armature of a capacitor consisting of a doped zone of a semiconductor substrate (1), and a gaseous dielectric layer (6) separating the two armatures. The membrane is deformed under the effect of the Lorentz force generated by a magnetic field located in the plane of the membrane and perpendicular to the current lines. The invention also concerns a method for making said magnetic sensor and a device for measuring magnetic field.

公开(公告)号：FR2799305B1

公开(公告)日：2004-06-18

申请号：FR9912406

申请日：1999-10-05

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA

IPC: H01L21/336 ,  H01L29/786

Abstract: Gate-all-around (GAA) architecture semiconductor device production, by gate formation around a bridge structure formed by removing material below a silicon layer (5) having a thin single crystal central portion (5a), is new. A semiconductor device of GAA architecture is produced from a substrate (1) having a central active semiconductor region (2) surrounded by a peripheral insulating region (3) by (a) selective epitaxy of a single crystal Ge or SiGe alloy layer on the active region main surface; (b) non-selective epitaxy of a silicon layer (5) which is monocrystalline above the single crystal layer and which is polycrystalline above the insulating region surface; (c) masking and etching of the silicon layer (5) and the single crystal layer to form, on the active region main surface, a stack with two opposite side walls exposing the single crystal layer; (d) selective etching away of the single crystal layer so that the silicon layer forms a bridge structure having side walls, an external surface and an internal surface defining, with the active region main surface, a tunnel (7); (e) formation of a dielectric thin film (8, 9), which does not fill the tunnel, on the external and internal surfaces and on the side walls of the bridge structure; (f) deposition of conductive material to cover the bridge structure and to fill the tunnel; and (g) masking and etching of the conductive material to form an all-around gate region (10) of desired dimensions and geometry. An Independent claim is also included for a semiconductor device produced by the above process, the central part (5a) of the bridge structure (5) being of single crystal silicon and being 1-50 nm thick.

公开(公告)号：FR2800913A1

公开(公告)日：2001-05-11

申请号：FR9914105

申请日：1999-11-10

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  MALLARDEAU CATHERINE

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/92 ,  H01G4/33 ,  H01G4/38

Abstract: The invention concerns a method which consists in forming on a substrate coated with a dielectric material layer provided with a window a stack of successive layers alternately of germanium or SiGe alloy and polycrystalline silicon; selective partial elimination of the germanium or SiGe alloy layers, to form an arborescent structure; forming a thin layer of dielectric material on the arborescent structure; and coating the arborescent structure with polycrystalline silicon. The invention is useful for making direct access dynamic memories.

公开(公告)号：FR2799305A1

公开(公告)日：2001-04-06

申请号：FR9912406

申请日：1999-10-05

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA

IPC: H01L21/336 ,  H01L29/786

Abstract: Gate-all-around (GAA) architecture semiconductor device production, by gate formation around a bridge structure formed by removing material below a silicon layer (5) having a thin single crystal central portion (5a), is new. A semiconductor device of GAA architecture is produced from a substrate (1) having a central active semiconductor region (2) surrounded by a peripheral insulating region (3) by (a) selective epitaxy of a single crystal Ge or SiGe alloy layer on the active region main surface; (b) non-selective epitaxy of a silicon layer (5) which is monocrystalline above the single crystal layer and which is polycrystalline above the insulating region surface; (c) masking and etching of the silicon layer (5) and the single crystal layer to form, on the active region main surface, a stack with two opposite side walls exposing the single crystal layer; (d) selective etching away of the single crystal layer so that the silicon layer forms a bridge structure having side walls, an external surface and an internal surface defining, with the active region main surface, a tunnel (7); (e) formation of a dielectric thin film (8, 9), which does not fill the tunnel, on the external and internal surfaces and on the side walls of the bridge structure; (f) deposition of conductive material to cover the bridge structure and to fill the tunnel; and (g) masking and etching of the conductive material to form an all-around gate region (10) of desired dimensions and geometry. An Independent claim is also included for a semiconductor device produced by the above process, the central part (5a) of the bridge structure (5) being of single crystal silicon and being 1-50 nm thick.

公开(公告)号：FR2801970B1

公开(公告)日：2002-02-15

申请号：FR9915410

申请日：1999-12-07

Applicant: ST MICROELECTRONICS SA

Inventor： JAOUEN HERVE ,  SKOTNICKI THOMAS ,  JURCZAK MALGORZATA

IPC: G01D5/242 ,  G01L9/00 ,  G10K9/13 ,  G01D5/241 ,  H01L43/12

Abstract: A magnetic sensor includes a thin deformable membrane made of a conductive material forming a first plate of a capacitor which conducts an electric current therethrough. A second capacitor plate of the capacitor includes a doped region of a semiconductor substrate. A layer of a gaseous dielectric separates the two plates. The membrane deforms due to the effect of the Lorentz force generated by a magnetic field lying in the plane of the membrane and perpendicular to the lines of current being conducted therethrough. In addition, a process for fabricating this magnetic sensor is also provided as well as a device for measuring a magnetic field using the magnetic sensor.

公开(公告)号：FR2806833A1

公开(公告)日：2001-09-28

申请号：FR0003844

申请日：2000-03-27

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  HAOND MICHEL

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/78

Abstract: MOS transistor production includes: forming first gate (2) in silicon-on-insulator substrate (1); forming semiconducting channel region transversely surmounting first gate, and drain (16) and source (17) regions respectively on each side of channel region; isolating channel region from upper surface of first gate; and forming the second gate (10) on, and transversely to, the channel region. Fabrication of a MOS transistor comprising a channel region sandwiched between a first gate (2) and a second gate (10) includes: (a) forming the first gate (2) in the body of a silicon-on-insulator (SOI) substrate (1); (b) on the upper surface of the substrate, forming by epitaxy a semiconducting channel region transversely surmounting the first gate (2), and semiconducting drain (16) and source (17) regions arranged respectively on each side of the channel region; (c) isolating the channel region from the upper surface of the first gate (2) by forming a tunnel under the channel region, and then filling it, at least partially, with a first dielectric material (8); and (d) forming the second gate (10) on the channel region and transversely to channel region, the second gate being separated from the upper surface of the channel region by a second dielectric material (8). An Independent claim is given for a MOS transistor produced by the above process. The thickness of dielectric material filling the tunnel produced in the MOS transistor is 1-50 nm, e.g. 20 nm.

公开(公告)号：FR2802705A1

公开(公告)日：2001-06-22

申请号：FR9915902

申请日：1999-12-16

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  DUTARTRE DIDIER

IPC: H01L21/20 ,  H01L21/762 ,  H01L29/06 ,  H01L21/3213 ,  B82B1/00 ,  B82B3/00

Abstract: The process for fabricating a network of nanometric lines made of single-crystal silicon on an isolating substrate includes the production of a substrate comprising a silicon body having a lateral isolation defining a central part in the body. A recess is formed in the central part having a bottom wall made of dielectric material, a first pair of opposed parallel sidewalls made of dielectric material, and a second pair of opposed parallel sidewalls. At least one of the opposed parallel sidewalls of the second pair being formed from single-crystal silicon. The method further includes the epitaxial growth in the recess, from the sidewall made of single-crystal silicon of the recess, of an alternating network of parallel lines made of single-crystal SiGe alloy and of single-crystal silicon. Also, the lines made of single-crystal SiGe alloy are etched to form in the recess a network of parallel lines made of single-crystal silicon insulated from each other.

公开(公告)号：FR2801971A1

公开(公告)日：2001-06-08

申请号：FR0003547

申请日：2000-03-20

Applicant: ST MICROELECTRONICS SA

Inventor： JAOUEN HERVE ,  JURCZAK MALGORZATA ,  SKOTNICKI THOMAS

IPC: H01L23/28 ,  G01D5/242 ,  G01L9/00 ,  G01S7/521 ,  G10K9/13 ,  H04R7/00 ,  H04R9/00 ,  H04R19/00 ,  H04R31/00 ,  G01D5/241 ,  H01L43/12

Abstract: The invention concerns a transmitter and receiver comprising several transducers arranged opposite an opening of a housing. Each transducer comprises a deformable semiconductor membrane (MB) designed to be run through by an electric current and separated by a substrate zone (ZSB1, ZSB2) by a cavity enabling the membrane to be deformed under the effect of acoustic pressure of a Lorenz force.