公开(公告)号：WO0135448A2

公开(公告)日：2001-05-17

申请号：PCT/FR0003153

申请日：2000-11-10

Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM ,  SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  MALLARDEAU CATHERINE

Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  MALLARDEAU CATHERINE

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/60

Abstract: The invention concerns a method which consists in forming on a substrate (1) coated with a dielectric material layer (3) provided with a window (3a), a stack of successive layers alternately of germanium or SiGe alloy (4, 6, 8) and polycrystalline silicon (5, 7, 9); selective partial elimination of the germanium or SiGe alloy layers, to form an tree-like structure; forming a thin layer of dielectric material (10) on the tree-like structure; and coating the tree-like structure with polycrystalline silicon (11). The invention is useful for making dynamic random-access memories.

Abstract translation: 本发明涉及一种方法，该方法包括在涂覆有设置有窗口（3a）的介电材料层（3）的基底（1）上，交替地具有锗或SiGe合金（4,6,8）的叠层， 和多晶硅（5,7,9）; 选择性地部分消除锗或SiGe合金层，形成树状结构; 在树状结构上形成介电材料薄层（10）; 并用多晶硅（11）涂覆树状结构。 本发明对于制作动态随机存取存储器是有用的。

公开(公告)号：FR2810452B1

公开(公告)日：2003-09-12

申请号：FR0007874

申请日：2000-06-20

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  MALLARDEAU CATHERINE

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/423 ,  H01L29/788 ,  H01L27/115 ,  G11C16/02

公开(公告)号：FR2828766A1

公开(公告)日：2003-02-21

申请号：FR0110866

申请日：2001-08-16

Applicant: ST MICROELECTRONICS SA

Inventor： MALLARDEAU CATHERINE ,  MAZOYER PASCALE ,  PIAZZA MARC

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/108 ,  H01L23/498 ,  H01L21/60

Abstract: There is provided an integrated circuit having active components including junctions formed in a monocrystalline substrate doped locally, and at least one passive component situated above the active components. The integrated circuit includes a first insulating layer separating the active components and abase of the passive component, and a metal terminal for electrically connecting the passive component with at least one of the active components. The metal terminal is formed in the thickness of the first insulating layer and has a contact surface that projects from the limits of a junction of the one active component. In a preferred embodiment, the passive component is a capacitor. Also provided is a method of fabricating an integrated circuit that includes MOS transistors and an onboard memory plane of DRAM cells in a matrix.

公开(公告)号：FR2828766B1

公开(公告)日：2004-01-16

申请号：FR0110866

申请日：2001-08-16

Applicant: ST MICROELECTRONICS SA

Inventor： MALLARDEAU CATHERINE ,  MAZOYER PASCALE ,  PIAZZA MARC

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/108 ,  H01L23/498 ,  H01L21/60

Abstract: There is provided an integrated circuit having active components including junctions formed in a monocrystalline substrate doped locally, and at least one passive component situated above the active components. The integrated circuit includes a first insulating layer separating the active components and abase of the passive component, and a metal terminal for electrically connecting the passive component with at least one of the active components. The metal terminal is formed in the thickness of the first insulating layer and has a contact surface that projects from the limits of a junction of the one active component. In a preferred embodiment, the passive component is a capacitor. Also provided is a method of fabricating an integrated circuit that includes MOS transistors and an onboard memory plane of DRAM cells in a matrix.

公开(公告)号：FR2828764A1

公开(公告)日：2003-02-21

申请号：FR0110868

申请日：2001-08-16

Applicant: ST MICROELECTRONICS SA

Inventor： MALLARDEAU CATHERINE ,  MAZOYER PASCALE ,  PIAZZA MARC

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

Abstract: The invention relates to an integrated circuit comprising: a capacitor (23) which is disposed on top of a substrate (1) inside a first cavity in a dielectric material; a first electrode; a second electrode; a fine dielectric layer which is disposed between the two electrodes; and a structure (7) which connects to the capacitor. Said connecting structure is disposed at the same level as the capacitor in a second cavity which is narrower than the first, said second cavity being entirely filled up by an extension of at least one of the electrodes of the capacitor.

公开(公告)号：FR2819341A1

公开(公告)日：2002-07-12

申请号：FR0100295

申请日：2001-01-11

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  MONFRAY STEPHANE ,  MALLARDEAU CATHERINE

IPC: H01L21/8242 ,  H01L27/108

Abstract: A process for making a DRAM-type cell includes growing layers of silicon germanium and layers of silicon, by epitaxy from a silicon substrate; superposing a first layer of N+ doped silicon and a second layer of P doped silicon; and forming a transistor on the silicon substrate. The method also includes etching a trench in the extension of the transistor to provide an access to the silicon germanium layers relative to the silicon layers over a pre-set depth to form lateral cavities, and forming a capacitor in the trench and in the lateral cavities.

公开(公告)号：FR2800913A1

公开(公告)日：2001-05-11

申请号：FR9914105

申请日：1999-11-10

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  MALLARDEAU CATHERINE

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/92 ,  H01G4/33 ,  H01G4/38

Abstract: The invention concerns a method which consists in forming on a substrate coated with a dielectric material layer provided with a window a stack of successive layers alternately of germanium or SiGe alloy and polycrystalline silicon; selective partial elimination of the germanium or SiGe alloy layers, to form an arborescent structure; forming a thin layer of dielectric material on the arborescent structure; and coating the arborescent structure with polycrystalline silicon. The invention is useful for making direct access dynamic memories.

公开(公告)号：FR2800913B1

公开(公告)日：2004-09-03

申请号：FR9914105

申请日：1999-11-10

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  MALLARDEAU CATHERINE

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/92 ,  H01G4/33 ,  H01G4/38

Abstract: The invention concerns a method which consists in forming on a substrate ( 1 ) coated with a dielectric material layer ( 3 ) provided with a window ( 3 a), a stack of successive layers alternately of germanium or SiGe alloy ( 4, 6, 8 ) and polycrystalline silicon ( 5, 7, 9 ); selective partial elimination of the germanium or SiGe alloy layers, to form an tree-like structure; forming a thin layer of dielectric material ( 10 ) on the tree-like structure; and coating the tree-like structure with polycrystalline silicon ( 11 ). The invention is useful for making dynamic random-access memories.

公开(公告)号：FR2828764B1

公开(公告)日：2004-01-23

申请号：FR0110868

申请日：2001-08-16

Applicant: ST MICROELECTRONICS SA

Inventor： MALLARDEAU CATHERINE ,  MAZOYER PASCALE ,  PIAZZA MARC

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

Abstract: This integrated circuit comprises a capacitor ( 23 ) formed above a substrate ( 1 ) inside a first cavity in a dielectric and comprising a first electrode, a second electrode, a thin dielectric layer placed between the two electrodes, and a structure ( 7 ) for connection to the capacitor. The connection structure is formed at the same level as the capacitor in a second cavity narrower than the first cavity, the said second cavity being completely filled by an extension of at least one of the electrodes of the capacitor.

公开(公告)号：FR2819341B1

公开(公告)日：2003-06-27

申请号：FR0100295

申请日：2001-01-11

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  MONFRAY STEPHANE ,  MALLARDEAU CATHERINE

IPC: H01L21/8242 ,  H01L27/108

Abstract: A process for making a DRAM-type cell includes growing layers of silicon germanium and layers of silicon, by epitaxy from a silicon substrate; superposing a first layer of N+ doped silicon and a second layer of P doped silicon; and forming a transistor on the silicon substrate. The method also includes etching a trench in the extension of the transistor to provide an access to the silicon germanium layers relative to the silicon layers over a pre-set depth to form lateral cavities, and forming a capacitor in the trench and in the lateral cavities.