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    1.
    发明专利
    未知

    公开(公告)号：FR2812764B1

    公开(公告)日：2003-01-24

    申请号：FR0010176

    申请日：2000-08-02

    Applicant: ST MICROELECTRONICS SA

    Inventor： SKOTNICKI THOMAS ,  HAOND MICHEL ,  DUTARTRE DIDIER

    IPC: H01L21/762 ,  H01L21/328

    Abstract: Processes are provided for fabricating a substrate having a silicon-on-insulator (SOI) or silicon-on-nothing (SON) architecture, which are applicable to the manufacture of semiconductor devices, especially transistors such as those of the MOS, CMOS, BICMOS, and HCMOS types. In the fabrication processes, a multilayer stack is grown on a substrate by non-selective full-wafer epitaxy. The multilayer stack includes a silicon layer on a Ge or SiGe layer. Active regions are defined and masked, and insulating pads are formed so as to be located around the perimeter of each of the active regions at predetermined intervals and placed against the sidewalls of the active regions. The insulating trenches are etched, and the SiGe or Ge layer is laterally etched so as to form an empty tunnel under the silicon layer. The trenches are filled with a dielectric. In the case of an SOI archiutecture, the tunnel is filled with a dielectric.

    2.
    发明专利
    未知

    公开(公告)号：FR2803092B1

    公开(公告)日：2002-11-29

    申请号：FR9916488

    申请日：1999-12-24

    Applicant: ST MICROELECTRONICS SA

    Inventor： TORRES JOAQUIM ,  GAYET PHILIPPE ,  HAOND MICHEL

    IPC: H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L21/28 ,  H01L23/528

    Abstract: One embodiment of the invention is directed to a method of forming a metallization level of an integrated circuit including the steps of forming metal areas of a metallization level laterally separated by a first insulating layer, removing the first insulating layer, non-conformally depositing a second insulating layer so that gaps can form between neighboring metal areas, or to obtain a porous layer. The removal of the first insulating layer is performed through a mask, to leave in place guard areas of the first insulating layer around the portions of the metal areas intended for being contacted by a via crossing the second insulating layer.

    Adjustment of transistor gate resistance in an integrated circuit involves exposing polysilicon of initial gate, forming gate extension by selective epitaxial deposition of a polysilicon layer, and siliciding the gate extension
    3.
    发明专利
    Adjustment of transistor gate resistance in an integrated circuit involves exposing polysilicon of initial gate, forming gate extension by selective epitaxial deposition of a polysilicon layer, and siliciding the gate extension 未知

    公开(公告)号：FR2804793A1

    公开(公告)日：2001-08-10

    申请号：FR0001484

    申请日：2000-02-07

    Applicant: ST MICROELECTRONICS SA

    Inventor： HAOND MICHEL

    IPC: H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/71 ,  H01L21/331 ,  H01L27/04

    Abstract: Adjustment of gate resistance of a transistor produced in a semiconductor substrate and covered with an insulating layer comprises: exposing the polysilicon of the initial gate (G1) of transistor (T1) surrounded by spacers (E1); forming a gate extension (GX1) by selective epitaxial deposition of a polysilicon layer; and siliciding at least part of the gate extension (GX1), to form a final gate. Preferred Features: The gate extension (GX1) is made to project laterally with respect to the initial gate. The whole of the gate extension (GX1) is preferably silicided. The process can be applied to an integrated circuit having complementary transistors, where each stage of the process is carried out simultaneously for all the transistors of the integrated circuit. An independent claim is given for an integrated circuit comprising at least one transistor produced in a semiconductor substrate and containing a silicided gate, where the gate comprises a lower part (G1) surrounded by insolating spacers (E1), and a gate extension (GX1) located above the lower part (G1) and covered at least partially with a metal silicide layer (GXS1). Preferably, the gate extension (GX1) covered with the metal silicide layer (GXS1) is larger than the lower part (G1) of the gate.

    4.
    发明专利
    未知

    公开(公告)号：DE69935401T2

    公开(公告)日：2007-11-29

    申请号：DE69935401

    申请日：1999-10-01

    Applicant: ST MICROELECTRONICS SA

    Inventor： ALIEU JEROME ,  LAIR CHRISTOPHE ,  HAOND MICHEL

    IPC: H01L21/768 ,  H01L23/522

    Abstract: The device and process include the deposition of polycrystalline germanium in the interconnect spaces between conductive metal elements. The device and process further include the removal of the germanium in order to form air-filled interconnect spaces.

    Method for implementing insulated metallic interconnections in integrated circuits
    6.
    发明专利
    Method for implementing insulated metallic interconnections in integrated circuits 未知

    公开(公告)号：FR2803093A1

    公开(公告)日：2001-06-29

    申请号：FR9916489

    申请日：1999-12-24

    Applicant: ST MICROELECTRONICS SA

    Inventor： GAYET PHILIPPE ,  TORRES JOAQUIM ,  HAOND MICHEL

    IPC: H01L21/768 ,  H01L21/28 ,  H01L23/528

    Abstract: The method for the formation of a metallization level in an integrated circuit comprises the following steps: the formaton of metallic zones (11-14) of that level separated laterally by a first insulator layer (6), the elimination of first insulator layer, and the deposition of a second insulator layer (24) in a nonuniform fashion to have cavities (26) formed between neighbouring metallic zones. The elimination of the first insulator layer is done through a mask in a manner to leave in place the portions (22) of the first insulator layer outside the regions where the metallic zones are close to one another. The feedthroughs or vias in layers (2,3) and (6,24) are filled with metal (4,30), and guard zones (21) ensure that there is no spreading of metal to neighbouring cavities. The semiconductor structure can contain two levels of metallization, and the cavities at two levels can be connected in pairs. In a variant of the method, a porous material as eg. aerogel or xerogel is deposited in a thickness sufficient to fill in all space between metallic zones (11-14) and slightly to overflow, which is covered by an insulator layer of standard structure. In another variant of the method, the mask is discontinuous and has substantially the same step as that of closely spaced metallic zones.

    10.
    发明专利
    未知

    公开(公告)号：FR2818012B1

    公开(公告)日：2003-02-21

    申请号：FR0016174

    申请日：2000-12-12

    Applicant: ST MICROELECTRONICS SA

    Inventor： SKOTNICKI THOMAS ,  MONFRAY STEPHANE ,  HAOND MICHEL

    IPC: H01L29/06 ,  H01L29/10 ,  H01L29/80 ,  H01L27/105

    Abstract: An electronic device, such as an opto-electronic device and an integrated semiconductor memory device, includes at least one integrated memory point structure including a quantum well semiconductor area buried in the substrate of the structure and disposed under the insulated gate of a transistor. A biasing voltage source is adapted to bias the structure to enable charging or discharging of charges in the quantum well or outside the quantum well.

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